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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
PM7350
DSLAM
REFERENCE DESIGN
LINE CARD
RELEASED ISSUE 3: NOVEMBER 2000
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
REVISION HISTORY Issue No. 1 2 Issue Date Apr 1999 Details of Change Document created.
Aug 1999 Changed name from S/UNI-DUPLEX Reference Design to DSLAM Reference Design: Line Card. Added register configurations. Added FPGA Design. Added schematics. Revised description of timing distribution.
3
Nov 2000 Changed status to Released. Added Layout. Back-annotated schematics. Added Bill of Materials. Added FPGA Code. Revised COMET register configuration.
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
CONTENTS 1 2 3 4 5 DEFINITIONS .......................................................................................... 1 FEATURES .............................................................................................. 2 REFERENCES......................................................................................... 3 SCOPE .................................................................................................... 4 BLOCK DIAGRAM ................................................................................... 5 5.1 5.2 6 S/UNI-DUPLEX ARCHITECTURE ................................................ 5 S/UNI-DUPLEX LINE CARD ......................................................... 5
FUNCTIONAL DESCRIPTION................................................................. 7 6.1 6.2 6.3 6.4 6.5 6.6 S/UNI-DUPLEX ............................................................................. 7 COMET ......................................................................................... 7 MICROPROCESSOR BLOCK ...................................................... 9 TIMING.......................................................................................... 9 POWER BLOCK ......................................................................... 10 CONNECTORS ........................................................................... 10
7
IMPLEMENTATION DESCRIPTION ...................................................... 12 7.1 S/UNI-DUPLEX DESIGN CONSIDERATIONS............................ 12 7.1.1 SCIANY PIN ..................................................................... 12 7.1.2 REGISTER CONFIGURATION ........................................ 12 7.1.3 POWER SUPPLY ............................................................. 13 7.1.4 DECOUPLING .................................................................. 13 7.1.5 OCTET ALIGNMENT........................................................ 13 7.2 COMET DESIGN CONSIDERATIONS........................................ 14
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
7.2.1 REGISTER CONFIGURATION ........................................ 14 7.2.2 POWER SUPPLY ............................................................. 15 7.2.3 DECOUPLING .................................................................. 16 7.3 7.4 7.5 7.6 7.7 7.8 7.9 8 MICROPROCESSOR INTERFACE ............................................ 16 REFERENCE TIMING DISTRIBUTION ...................................... 17 FPGA DESIGN ............................................................................ 18 LED DESCRIPTION.................................................................... 21 JUMPER CONFIGURATION....................................................... 21 HOT SWAP DESIGN NOTES ..................................................... 22 LVDS DESIGN NOTES ............................................................... 22
BOARD MODIFICATIONS ..................................................................... 25
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
LIST OF FIGURES FIGURE 1 - DSLAM LINE CARD ARCHITECTURES ....................................... 5 FIGURE 2 - DSLAM LINE CARD BLOCK DIAGRAM........................................ 6 FIGURE 3 - MICROPROCESSOR BLOCK DIAGRAM ................................... 17 FIGURE 4 - 8KHZ TIMING OPTIONS ............................................................. 18 FIGURE 5 - LVDS BACKPLANE TERMINATION SCHEME ........................... 23 FIGURE 6 - LVDS FRONT PANEL TERMINATION SCHEME ........................ 24
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iii
RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
LIST OF TABLES TABLE 1 TABLE 2 TABLE 3 TABLE 4 TABLE 5 TABLE 6 TABLE 7 TABLE 8 - S/UNI-DUPLEX REGISTER CONFIGURATION.......................... 12 - COMET REGISTER CONFIGURATION...................................... 14 - COMET TCLK SELECTION (0X00H - 0X01H) ........................... 18 - CLOCK SOURCE SELECT BITS ................................................ 19 - S/UNI-DUPLEX TX8K SELECTION (0X02H) .............................. 19 - CLOCK SOURCE SELECT BITS ................................................ 20 - COMET STATUS LEDS (0X03H)................................................. 20 - BILL OF MATERIALS .................................................................. 37
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
1
DEFINITIONS ADSL ATM CABGA CO COMET DSLAM LAN LVDS PBGA POTS PSTN S/UNI S/UNI-APEX S/UNI-DUPLEX S/UNI-VORTEX WAN Asymmetric Digital Subscriber Line Asynchronous Transfer Mode Chip Array Ball Grid Array Central Office PMC-Sierra's mnemonic for the PM4351 Combined E1/T1 Framer/Transceiver Digital Subscriber Line Access Multiplexer Local Area Network Low Voltage Differential Signal Plastic Ball Grid Array Plain Old Telephone Service Public Switched Telephone Network SATURN User Network Interface PMC-Sierra's mnemonic for the PM7326 ATM/PACKET Traffic Manager and Switch PMC-Sierra's mnemonic for the PM7350 Dual Port Serialized UTOPIA Multiplexer PMC-Sierra's mnemonic for the PM7351 Eight Port Serialized UTOPIA Multiplexer Wide Area Network
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
2
FEATURES * * * * * * * * * * * A reference design of the Line Card portion of a DSLAM system. Showcases a high-density architecture with the PBGA S/UNI-DUPLEX and CABGA COMET devices. Supports 16 serial interfaces to transport ATM over T1/E1. Contains short-haul (intra-building) protection circuitry for high-speed telecommunication lines. A high-speed LVDS Interface capable of data rates up to 200 MB/s. Supports 1:1 protection switching to a Core Card. Allows clock synchronization through the use of an embedded reference clock. A serial interface to the onboard microprocessor to configure, control and monitor the S/UNI-DUPLEX and COMET devices. An embedded inter-device communications channel, allowing devices on the Core Card to communicate with devices on the Line Card. Supports hot swap capability to allow live insertion/extraction. CompactPCI (cPCI) compatible.
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
3
REFERENCES 1. PCI Industrial Computers Manufacturers Group (PICMG), "CompactPCI Specification 2.0 R 2.1", Wakefield MA, September 1997. 2. PMC-Sierra Inc., PMC-1970624, "COMET - Combined E1/T1 Transceiver/Framer Long Form Data Sheet", July 1999, Issue 8. 3. PMC-Sierra Inc., PMC-1981025, "S/UNI-VORTEX and S/UNI-DUPLEX Technical Overview", June 1999, Issue 2. 4. PMC-Sierra Inc., PMC-1980581, "S/UNI-DUPLEX Dual Serial Link PHY Multiplexer Data Sheet", April 2000, Issue 5. 5. PMC-Sierra Inc., PMC-1990832, "DSLAM Reference Design: System Design", September 2000, Issue 3. 6. PMC-Sierra Inc., PMC-1990815, "DSLAM Reference Design: Core Card", September 2000, Issue 3. 7. PMC-Sierra Inc., PMC-1990474, "DSLAM Reference Design: WAN Card", September 2000, Issue 3.
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
4
SCOPE The purpose of this reference design is to assist engineers in designing their products using PMC-Sierra's S/UNI-DUPLEX device. The DSLAM Reference Design is composed of the following four documents: * * * * DSLAM Reference Design: System Design DSLAM Reference Design: Core Card DSLAM Reference Design: Line Card DSLAM Reference Design: WAN Card
The DSLAM Reference Design: System Design document provides an overview of the DSLAM system architecture. The remaining documents describe the functionality and implementation specific details for each individual card. This document only describes designs for the DSLAM Line Card based on the S/UNI-DUPLEX device. A block diagram is shown for the design. A description is then given for the functional blocks of the design. A detailed implementation description then follows.
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
5 5.1
BLOCK DIAGRAM S/UNI-DUPLEX Architecture The S/UNI-DUPLEX provides a SCI-PHY/Any-PHY interface or a clocked serial data interface. The use of the SCI-PHY/Any-PHY interface and the clocked serial data interface is mutually exclusive due to the fact that many signals of these two interfaces share physical package pins. Therefore, it is this interface that defines the architecture of the Line Card. Figure 1 shows the two possible Line Card architectures based on the PHY/FRAMER interfaces. Figure 1 - DSLAM Line Card Architectures UTOPIA Line cards
xDSL PHY
S/UNIDUPLEX
xDSL PHY
processor
Clock/Data Line cards
COMET
S/UNIDUPLEX
COMET
processor
This reference design is based on the serial clock and data architecture. An example of the UTOPIA bus architecture is left for the DSLAM Reference Design: WAN Card [8]. 5.2 S/UNI-DUPLEX Line Card A block diagram for this design is shown in Figure 2. For upstream traffic, a highdensity connector transports 16 T1/E1 lines onto the board. The 16 T1/E1 line inputs are connected to 16 COMET devices. The clock and data lines from each COMET are then connected to the S/UNI-DUPLEX. The S/UNI-DUPLEX takes the clocked serial data and multiplexes the data onto the high-speed LVDS
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
interface. This high-speed LVDS interface transports data to the Core Card. For downstream traffic, the Core Card transmits data for the 16 physical interfaces through the high-speed LVDS interface. The S/UNI-DUPLEX receives the LVDS data and demultiplexes the LVDS data. It is then sent to the COMET for transmission over the T1/E1 interface. Figure 2 - DSLAM Line Card Block Diagram
4 4
S/UNIDUPLEX
64
J5
COMET COMET
LVDS
Oscillators
LVDS QUAD TXFMR
COMET
COMET
COMET
COMET
High Density Line Interface Connector for TIP/RING
QUAD TXFMR
COMET
COMET
64
COMET COMET
QUAD TXFMR
COMET COMET
QUAD TXFMR
COMET
COMET
3.3V Regulator Hot Swap Controller
Power Block
COMET
COMET
Data
RJ-45 RS-232 ROM RAM RAM
Address
Microprocessor Block
Oscillators Micro
FPGA
J1
BDM PORT
This design illustrates the S/UNI-DUPLEX interface for clocked serial data. Full serial fan-in potential of the S/UNI-DUPLEX device is demonstrated.
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
6
FUNCTIONAL DESCRIPTION The following sections describe the functional blocks of the block diagram shown in Figure 2.
6.1
S/UNI-DUPLEX The PM7350 S/UNI-DUPLEX is a monolithic integrated circuit typically used for traffic concentration within a Digital Subscriber Line Access Multiplexer (DSLAM). The device is ATM specific. It exchanges contiguous 53 byte cells with PHY devices. The PHY interface can be either clocked serial data or SCI-PHY/AnyPHY. With a clocked serial data configuration up to sixteen channels are supported. Cell alignment is established through HCS (Header Check Sequence) delineation. The cell payload is scrambled and descrambled with a x43 + 1 polynomial. Rate adaptation is performed through idle cell insertion and extraction. Each PHY interface has a dedicated four cell FIFO in both upstream and downstream directions. All cell streams are multiplexed into a high-speed serial stream. The high-speed interfaces use NRZ data-only differential signals compatible with LVDS levels. The internal transmit clock is synthesized from a lower frequency reference. An extended cell format provides four extra bytes for the encoding of flow control, timing reference, PHY identification and link maintenance information. A redundant link is provided to allow connection to two cell processing cards. A microprocessor port provides access to internal configuration and monitoring registers. The port may also be used to insert and extract cells in support of a control channel. For further information, please see the S/UNI-DUPLEX Datasheet PMC-1980581 [5].
6.2
COMET The PM4351 Combined E1/T1 Transceiver (COMET) is a feature-rich monolithic integrated circuit suitable for use in long haul and short haul T1 and E1 systems with a minimum of external circuitry. The COMET is software configurable, allowing feature selection without changes to external wiring. Analog circuitry is provided to allow direct reception of long haul E1 and T1 compatible signals with up to 43 dB cable loss (at 1.024 MHz in E1 mode) or up
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
to 36 dB cable loss (at 772 kHz in T1 mode) using a minimum of external components. Typically, only line protection, a transformer and a line termination resistor are required. Digital line inputs are provided for applications not requiring a physical T1 or E1 interface. The COMET recovers clock and data from the line and frames to incoming data. In T1 mode, it can frame to several DS-1 signal formats: SF, ESF, T1DM (DDS) and SLC(R)96. In E1 mode, the COMET frames to basic G.704 E1 signals and CRC-4 multiframe alignment signals, and automatically performs the G.706 interworking procedure. AMI, HDB3 and B8ZS line codes are supported. The COMET supports detection of various alarm conditions such as loss of signal, pulse density violation, Red alarm, Yellow alarm, and AIS alarm in T1 mode and loss of signal, loss of frame, loss of signaling multiframe and loss of CRC multiframe in E1 mode. The COMET also supports reception of remote alarm signal, remote multiframe alarm signal, alarm indication signal, and time slot 16 alarm indication signal in E1 mode. The presence of Yellow and AIS patterns in T1 mode and remote alarm and AIS patterns in E1 mode is detected and indicated. In T1 mode, the COMET integrates Yellow, Red, and AIS alarms as per industry specifications. In E1 mode, the COMET integrates Red and AIS alarms. In T1 mode, the COMET generates framing for SF, ESF and T1DM (DDS) formats. In E1 mode, the COMET generates framing for a basic G.704 E1 signal. The signaling multiframe alignment structure and the CRC multiframe structure may be optionally inserted. Framing can be optionally disabled. Internal analog circuitry allows direct transmission of long haul and short haul T1 and E1 compatible signals using a minimum of external components. Typically, only line protection, a transformer and an optional line termination resistor are required. Digitally programmable pulse shaping allows transmission of DSX-1 compatible signals up to 655 feet from the cross-connect, E1 short haul pulses into 120 ohm twisted pair or 75 ohm coaxial cable, E1 long haul pulses into 120 ohm twisted pair as well as long haul DS-1 pulses into 100 ohm twisted pair with integrated support for LBO filtering as required by the FCC rules. In addition, the programmable pulse shape extending over 5-bit periods allows customization of short haul and long haul line interface circuits to application requirements. Digital line inputs and outputs are provided for applications not requiring a physical T1 or E1 interface. In the transmit path, the COMET supports signaling insertion, idle code substitution, digital milliwatt tone substitution, data inversion, and zero code suppression on a per-channel basis. Zero code suppression may be configured to Bell (bit 7), GTE, or DDS standards, and can also be disabled. Transmit side
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
data and signaling trunk conditioning is also provided. Signaling bit transparency from the backplane may be enabled. The COMET provides optional jitter attenuation in both the transmit and receive directions. The COMET provides both a parallel microprocessor interface for controlling the operation of the device and serial PCM interfaces that allow backplane rates from 1.544 Mbit/s to 8.192 Mbit/s to be directly supported. For further information, please see the COMET Datasheet PMC-1970624 [3]. 6.3 Microprocessor Block An on-board microprocessor is used to monitor and control the S/UNI-DUPLEX and COMET devices. It requires the following features: * * * * * * 8-bit data bus Address bus Programmable chip selects Interrupt controller Serial interface Background Debug Module
The MC68340 was chosen for this reference design. An FPGA is used in the microprocessor block to provide the glue logic necessary to interface MC68340 to the PMC-Sierra devices. The FPGA will provide address decoding to generate the chip selects to all the PMC-Sierra devices. The FPGA will also be used as a buffer to balance the load on the address and data busses. The VHDL code for the FPGA is included in Appendix C. 6.4 Timing The timing block consists of the oscillators and part of the FPGA. Timing on the Line Card requires providing clock signals to 18 devices on the board: one S/UNI-DUPLEX, 16 COMETs and one MC68340.
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
The MC68340 requires two oscillators. A 25 MHz clock is needed for the processing core. A 3.6864 MHz clock is needed for the serial interface. Onboard oscillators provide these timing sources. The S/UNI-DUPLEX requires one jitter-free clock input for REFCLK. It is used as the reference clock by both clock recovery and clock synthesis circuits. The high-speed serial interface bit rate is eight times the REFCLK frequency. A 25 MHz on-board oscillator is used for this input. Each COMET requires a jitter-free clock input for XCLK to provide timing for internal circuitry. An on-board 2.048 MHz oscillator provides the XCLK input. The FPGA is used to distribute an 8 kHz reference clock. This reference timing for the PMC-Sierra devices is used to clock data throughout the system. Please refer to the DSLAM Reference Design: System Design [6] document for a thorough discussion on the use of the reference clock. 6.5 Power Block Power requirements of the board are +5V and +3.3V. +5V is available through J1 of the CompactPCI backplane. A linear regulator is used to regulate +3.3V from the +5V supply. Front panel LEDs will be used to indicate power status. A hot swap controller is used to manage the power of the board during insertion and removal. 6.6 Connectors There are two groups of connectors for the Line Card: the faceplate connectors and the backplane connectors. The faceplate connectors consist of the LVDS connectors, T1/E1 connector and the microprocessor serial interface connector. The backplane connectors are CPCI connectors J1 and J5. The LVDS connector requires a bandwidth of 100 to 200 Mb/s. The IEEE 1394 Firewire plug was chosen to meet both the bandwidth and board space requirements. It is used to carry the LVDS data from the Line Card to the Core Card over Firewire cables. The physical limitations of the CompactPCI board does not allow 16 T1/E1 transmit/receive interfaces to be placed in an accessible fashion on the front panel. Therefore, a high-density connector to accommodate the line interfaces is used. These can easily be moved to a rear I/O card on the rear of the CompactPCI shelf with the signals going through the CompactPCI backplane connectors. However, this would require a rear I/O board to be designed and manufactured and therefore is not included in this reference design.
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
The microprocessor serial interface connector is a RJ-45 style connector. It is used to communicate with the microprocessor through a simple serial interface such as a dumb terminal or Windows HyperTerminal. J1 is used to supply power and ground to the board only. All digital signals from the CPCI motherboard are left unconnected. J5 is used to transport the LVDS data from the Line Card to the Core Card over a backplane. This is an option of the Line Card and is configured through jumpers on the board.
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
7
IMPLEMENTATION DESCRIPTION The following sections describe detailed design considerations of the reference design.
7.1
S/UNI-DUPLEX Design Considerations
7.1.1 SCIANY Pin The SCI-PHY/Any-PHY Interface (SCIANY) input selects the type of PHY device interface. To configure the S/UNI-DUPLEX for clocked serial data, this pin must be a logic low. 7.1.2 Register Configuration On power-up or reset, the S/UNI-DUPLEX registers are reset to the default setting as described in the datasheet [5]. Table 1 shows the registers changed after reset. Table 1 Register 0x01h Master Configuration - S/UNI-DUPLEX Register Configuration Power-up Firmware Default Default 0x02h 0x26h Description LTXCINV = 1 Configures the serial data to update the TX on the falling edge of the clock. MINTE = 1 Turns on Master Interrupt Enable bit. 0x5Eh Transmit Logical Channel FIFO Depth 0x00h 0x04h FDEPTH[5:0] = 000100b For the Clocked Serial Data Interface, this FIFO depth is needed for correct operation.
Further configuration of the S/UNI-DUPLEX can be accomplished via the serial interface of the microprocessor.
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
7.1.3 Power Supply During power-up, the BIAS pin must be equal to or greater than the voltage on the VDD pins. This is accomplished with the voltage regulator. The voltage on the BIAS pin is also the same one used to regulate the VDD voltage. Therefore, the worst case is that the regulator malfunctions and shorts, which still leaves the BIAS pin equal to VDD. Also, an extra protection diode is used to limit the VDD to a maximum of 0.5V above the BIAS voltage. Analog power pins QAVD, CAVD, RAVD and TAVD must be applied after VDD or they must be current limited to the maximum latch-up current of 100mA. A simple solution is to use a small filtering network between VDD and the AVD pin to delay the power to the AVD pin. The differential voltage measured between AVD supplies and VDD must be less than 0.5V. 7.1.4 Decoupling A 0.01F or 0.1F capacitor is placed between power and ground for each VDD pin. The capacitor should be placed as close to the actual pin as possible. The AVD pins require a filtering network between the VDD supply and each AVD pin. The network is a single RC network with the resistor between the VDD supply and the AVD pin and the capacitor from the AVD pin to the GND plane. Please refer to the schematics in Appendix A for component values. 7.1.5 Octet Alignment The S/UNI-DUPLEX is configured for a bit-aligned interface with the COMET. This allows a glueless interface between the S/UNI-DUPLEX and COMET. To implement an octet-aligned interface with the COMET, the ALIGN bit must be set to 1 in Register 0x74: Transmit Serial Alignment Control. This configures the S/UNI-DUPLEX to output the most significant bit of the data octet during the gap period. LTXD[N] will then need to be delayed by one clock cycle in order to align the most significant bit of the octet to output as the first bit after the gap period. This can be accomplished by placing flip-flop into the data path to hold the data by one clock cycle.
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
7.2
COMET Design Considerations
7.2.1 Register Configuration On power-up or reset, the COMET registers are reset to the default setting as described in the datasheet [3]. Table 2 shows the registers changed after reset. Table 2
Register
- COMET Register Configuration
Power-up Default 0x00h Programmed Value see Datasheet Description of changes
0x0F2h XLPG Pulse Waveform Storage Write Address 0x0F3h XLPG Pulse Waveform Storage Data 0x000h Global Configuration 0x0F0 XLPG Line Driver Configuration 0x0D6 CSU Configuration 0x01C RX-ELST Configuration 0x020 TX-ELST Configuration 0x048 T1 FRMR Configuration 0x054 T1 XBAS Configuration 0x060 T1 ALMI Configuration 0x050 SIGX Configuration
The XLPG registers are modified for transmit waveform values corresponding to T1 Short Haul (0 - 110ft.).
0x00h
see Datasheet
0x80h
0x10h
Sets the PIO pin as input. Sets the RSYNC to use digital loss of signal. Sets the COMET devices to operate in T1 mode. Enables the XLPG and sets the SCALE[4..0] bits for T1 Short Haul (0 - 110ft.) Sets XCLK = 2.048MHz, TCLKO = 1.544MHz Configures for T1 mode. Configures for T1 mode. Enables ESF framing. Enables ESF framing and B8ZS Line Encoding. Enables ESF framing. Enables ESF framing.
0x80h
0x0Ch
0x00h 0x03h 0x03h 0x00h 0x00h 0x00h 0x00h
0x07h 0x00h 0x00h 0x30h 0x30h 0x10h 0x04h
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
Register
Power-up Default 0x38h
Programmed Value 0x00h
Description of changes
0x030 BRIF Configuration 0x031 BRIF Frame Pulse Configuration 0x032 BRIF Parity 0x0FF RLPS Equalizer Configuration 0x002 Receive Options 0x0DC RLPS Equalizer Voltage Reference 0x0D8-0x0DB and 0x0FD0x0FC Receive Equalizer Table
BRCLK is configured to be an output. BRPCM is updated on the falling edge.
0x20h
0x00h
Sets BTFP as frame pulse master.
0x00h 0x03h
0x01h 0x0Bh
Enables backplane data and signaling Enables Equalizer Feedback Loop.
0x80h 0x00h
0x00h 0x2Ch
Enables RJAT. Sets the voltage reference of the analog receive equalizer. The RLPS equalization table is set for T1.
0x00h
see Datasheet
Further configuration of the COMET can be accomplished via the serial interface of the microprocessor. 7.2.2 Power Supply During power-up, the BIAS pin must be equal to or greater than the voltage on the VDD pins. This is accomplished with the voltage regulator. The voltage on the BIAS pin is also the same one used to regulate the VDD voltage. Therefore, the worst case is that the regulator malfunctions and shorts, which still leaves the BIAS pin equal to VDD. Also, an extra protection diode is used to limit the VDD to a maximum of 0.5V above the BIAS voltage. Analog power pins must be applied after VDD or they must be current limited to the maximum latch-up current of 100mA. A simple solution is to use a small filtering network between VDD and the AVD pin to delay the power to the AVD pin.
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
The differential voltage measured between AVD supplies and VDD must be less than 0.5V. 7.2.3 Decoupling A 0.01F capacitor is placed between power and ground for the VDDO pins. A 0.1F capacitor is placed between power and ground for the VDDI pins. The capacitors should be placed as close to the actual pin as possible. The AVD pins require a filtering network between the VDD supply and each AVD pin. The network is a single RC network with the resistor between the VDD supply and the AVD pin and the capacitor from the AVD pin to the GND plane. Please refer to the schematics in Appendix A for component values. 7.3 Microprocessor Interface Figure 3 shows a block diagram of the microprocessor block and its interface with the PMC-Sierra devices.
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
Figure 3
- Microprocessor Block Diagram
A<23..0>
74FCT245
A<19..1>
RAM
D<15..8>
MC68340
A<23..0> A<19..1> D<15..0> D<7..0>
RAM
D<15..0>
74FCT245
CS0B CS1B CS2B A<18..1>
ROM
CS3B D<15..0>
R/WB SIZ0 D<15..8> A<23..0> DUPLEX_CSB RDB WRB
FPGA
CONTROL SIGNALS
D<7..0> A<7..0>
S/UNI DUPLEX
A<8..0> D<7..0> RDB WRB COMET_CSB<15..0>
COMET x 16
The MC68340 signals used to generate the chip select bits for the PMC-Sierra devices are CS2B and A<23..0>. The chip select logic is performed in the FPGA. The FPGA also provides a RDB and a WRB to the PMC-Sierra devices generated from R/WB of the microprocessor. Other control signals from the microprocessor are used to generate control signals for the RAM, ROM and debug port. The VHDL code for the FPGA is included in Appendix C. 7.4 Reference Timing Distribution The S/UNI-DUPLEX provides a method of transporting a reference clock over the LVDS connection. By using the TX8K and RX8K pins of the S/UNI-DUPLEX, a low speed reference clock can be sent or received respectively. This reference clock is typically an 8 kHz clock used for timing PCM voice circuitry. However, the reference clock is not constrained to 8 kHz, any frequency less than the cell rate is permissible.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
17
RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
The rising edge of TX8K initializes an internal counter to count the number of bytes in the high-speed serial cell being sent over the LVDS connection. The counter is encoded into the TREF[5..0] bits of the System Prepend Bytes of the LVDS ATM cell. An all ones value indicates no timing mark is associated with this cell. On the receiver side, the inherent jitter is at one octet. For example, at 155 MHz, the jitter is 52 ns, at 200 MHz it is 40 ns. For a discussion on system timing, please refer to the DSLAM Reference Design: System Design [6] document. 7.5 FPGA Design In this design, the FPGA is used to distribute an 8 kHz reference clock to devices on the board based on internal registers programmed into the FPGA. Figure 4 shows the different timing options available and the multiplexing performed by the FPGA. Figure 4 - 8kHz Timing Options
TCLKI<15..0>
RX8K
REFCLK
25 MHz Oscillator
COMET x 16
2.048 MHz Oscillator XCLK<15..0> RSYNC<15..0>
S/UNI DUPLEX
16
TX8K
The following registers are available on the FPGA: 0x00h-0x01h COMET TCLK Selection and 0x02h S/UNI-DUPLEX TX8K Selection. Table 3 Bit 7 Unused - COMET TCLK Selection (0x00h - 0x01h) Bit 6 Unused Bit 5 Unused Bit 4 C[5] Bit 3 C[4] Bit 2 C[3] Bit 1 C[2] Bit 0 C[1]
Register 0x00h - 0x01h selects the TCLK input for COMET #0 to COMET #7 and COMET #8 to COMET #15 respectively. Table 4 shows the use of the C[5..1] bits. Default for both TCLK Selection Registers are "10000", 2.048 MHz oscillator.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
18
RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
Table 4 C[5..0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 11111
- Clock Source select bits Clock Source Selected COMET #0 RSYNC COMET #1 RSYNC COMET #2 RSYNC COMET #3 RSYNC COMET #4 RSYNC COMET #5 RSYNC COMET #6 RSYNC COMET #7 RSYNC COMET #8 RSYNC COMET #9 RSYNC COMET #10 RSYNC COMET #11 RSYNC COMET #12 RSYNC COMET #13 RSYNC COMET #14 RSYNC COMET #15 RSYNC 2.048 MHz Oscillator S/UNI-DUPLEX RX8K
Table 5 Bit 7 Unused
- S/UNI-DUPLEX TX8K Selection (0x02h) Bit 6 Unused Bit 5 Unused Bit 4 Unused Bit 3 C[4] Bit 2 C[3] Bit 1 C[2] Bit 0 C[1]
Register 0x02h S/UNI-DUPLEX TX8K input selects the source for the TX8K pin of the S/UNI-DUPLEX. Table 6 shows the use of the C[4..1] bits. The default is "0000", COMET #0 RSYNC.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
19
RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
Table 6 C[4..0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
- Clock Source select bits Clock Source Selected COMET #0 RSYNC COMET #1 RSYNC COMET #2 RSYNC COMET #3 RSYNC COMET #4 RSYNC COMET #5 RSYNC COMET #6 RSYNC COMET #7 RSYNC COMET #8 RSYNC COMET #9 RSYNC COMET #10 RSYNC COMET #11 RSYNC COMET #12 RSYNC COMET #13 RSYNC COMET #14 RSYNC COMET #15 RSYNC
The FPGA also has the ability to control the COMET status LEDs. Table 7 shows register 0x03h of the FPGA. Table 7 Bit 7 Unused - COMET Status LEDs (0x03h) Bit 6 Unused Bit 5 Unused Bit 4 Unused Bit 3 C 1-4 Bit 2 C 5-8 Bit 1 C 9-12 Bit 0 C 13-16
The front panel LEDs are lit if the corresponding bit of the LED is set to "1".
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
20
RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
7.6
LED Description There are three sets of LEDs for the Line Card. The basic set of LEDs provides visual information about power and the microprocessor. * * * * +5 V, green - indicates presence of +5 V +3.3 V, green - indicates presence of +3.3 V uP, green - ON indicates trouble at uP (power-up boot) or RESET Heart Beat, green - indicates healthy uP interface to all components
Additional red LEDs indicate loss of signal and loss of cell delineation on the S/UNI-DUPLEX. * * * * LOS1, red - loss of signal at LVDS RXD1 LCD1, red - loss of cell delineation at LVDS RXD1 LOS2, red - loss of signal at LVDS RXD2 LCD2, red - loss of cell delineation at LVDS RXD2
LED indication loss of signal and loss of frame on the COMET devices are grouped by four. * * * * 7.7 C 1-4, red - loss of signal or frame at COMET 1 to 4 C 5-8, red - loss of signal or frame at COMET 5 to 8 C 9-12, red - loss of signal or frame at COMET 9 to 12 C 13-16, red - loss of signal or frame at COMET 13 to 16
Jumper Configuration There are two sets of jumpers on the board: LVDS and microprocessor. The LVDS jumpers are used to manually select the LVDS datapath. The LVDS can be configured to communicate through the front panel connectors or the backplane connectors.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
21
RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
The microprocessor jumpers are used to manually select whether the microprocessor runs from ROM or from the BDM port. 7.8 Hot Swap Design Notes When a board is plugged into a backplane, large transient currents can be drawn to charge up the bypass capacitors on the board. This can cause the voltage from the power supply to dip. The dip in voltage levels can cause other boards in the system to fail. Also, the connector pins may be damaged because they are not able to handle the large currents. The solution is to use an N-channel MOSFET transistor to ramp up the supply voltage in a controlled manner. A hot swap controller, the LTC1422 in this design, can be used to control the gate of the N-channel transistor. By ramping the voltage at a controlled rate, the transient surge current
I =C dV dt
is controlled and limited to a safe value when the board makes connection. 7.9 LVDS Design Notes The low voltage differential signals should be routed together. The two traces that form a differential TX/RX path should have equal trace lengths from the chip to the connector. This is so any coupling on the TX/RX path is common-mode and not differential. Traces for the LVDS signals should have controlled impedances. The two 49.9 differential receive termination resistors should be located as physically close to the chip as possible. There are two methods of termination for the LVDS signals, selectable through onboard jumpers. The first method, depicted in Figure 5, is used for LVDS lines that interface to the DSLAM backplane.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
22
RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
Figure 5
CORE CARD S/UNI-VORTEX
- LVDS Backplane Termination Scheme
LINE CARD S/UNI-DUPLEX DSLAM BACKPLANE
RXD+
49.9 49.9
50
TXD+
0.1 uF
50
RXDCORE CARD S/UNI-VORTEX DSLAM BACKPLANE
TXD-
LINE CARD S/UNI-DUPLEX
TXD+
50
49.9 49.9
RXD+
TXD-
50
0.1 uF
RXD-
Backplane Termination
The second method, depicted in Figure 6, is used for LVDS lines that interface to the front panel. Two additional termination methods are possible for front panel LVDS signals: * * Capacitive Coupling Transformer Coupling
Capacitive coupling, as indicated by the dashed lines offers a low cost, low board space alternative for LVDS signals that originate from shelves on the same ground system. To use the capacitive coupling option, do not install the transformers. Install the 0.22F and 1M resistors instead. For shelf to shelf termination where the shelves are on different ground systems, transformers are required to provide isolation. Common mode chokes are also used to reduce the amount of radiated and received electromagnetic interference (EMI). Only one end of the connection requires transformers. These transformers are not used on the Core cord due to the large number of transformers that would be required to interface to both the Line and WAN Cards. To use the transformer coupling option, do not install the 0.22 F or 1M resistors. Install the transformer instead.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
23
RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
Figure 6
CORE CARD S/UNI-VORTEX
- LVDS Front Panel Termination Scheme
Shelf to Shelf Termination
LVDS CABLE
0.22 uF 750
LINE CARD S/UNI-DUPLEX
3.3V
RXD+ 50
1M 49.9 49.9
TXD+
0.1 uF
430
0.1uF
50 RXD1M
1:1
TXD-
0.22 uF
CORE CARD S/UNI-VORTEX LVDS CABLE
3.3V 0.22 uF
LINE CARD S/UNI-DUPLEX
TXD+
50
1M 750
RXD+
49.9 0.1uF 49.9
430
TXD-
50
1M
1:1
RXD-
0.22 uF
0.1uF
In all termination methods, the LVDS receive signals are terminated by two 49.9 resistors and a 0.1uF capacitor. This termination network should be placed as physically close to the S/UNI-DUPLEX as possible.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
24
RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
8
BOARD MODIFICATIONS The following board modifications were made to the DSLAM Line Card. * * * * The R/WB trace to the FPGA U61 was missing from the layout. A wire from U42 pin 24 to U61 pin 74 reconnects R/WB to the FPGA. The FPGA internal registers were not reset on power-up. A wire from U65 pin 8 to U61 pin 112 labeled FPGA4 connects RESETB to the FPGA. Hot Swappable long pins are not installed so early power is not available. Resistors R31 and R32, both 0 , are not populated. After device characterization, filter circuits for the S/UNI-DUPLEX have been modified. Filter recommendations are: * * * * QAVD: R225 changed from 1.0k to 0, C45, 22uF, is removed. CAVD: R258 changed from 20 to 5, C50 changed from 22uF to 1uF. RAVD: R259 changed from 20 to 0, C51, 22uF, is removed. TAVD: R260 changed from 3.3 to 0, C52, 22uF, is removed.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
25
RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
APPENDIX A: SCHEMATICS This schematic contains 34 pages as follows: Sheet 1: Root Drawing This sheet provides a block view of the interface signals between each block of the DSLAM Line Card Reference Design. Sheet 2 - 3: S/UNI-DUPLEX Blocks These 2 sheets show the connections needed for the S/UNI-DUPLEX device. It also shows the interface for the LVDS connection. Sheet 4: CPCI Interface This sheet shows the cPCI connector J1 and the power supply circuit. It also contains the mechanical mounting and grounding needed for a cPCI board. Sheet 5: LVDS Interface This sheet contains the connector used to carry the LVDS signals across a backplane. Sheet 6: Microprocessor Block This sheet contains the Microprocessor and the signals used to interface the MC68340. Sheet 7 - 8: Microprocessor Interface These sheets show the devices necessary to complete an entire microprocessor interface including ROM, RAM and an FPGA for address decoding. Sheet 9: Front Panel This sheet shows the front panel connector for the 16 TIP/RING pairs used for the line interface to the COMET device. Sheet 10 - 17: Line Interface Blocks These 8 sheets contain the line interface to the COMET device.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
26
RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
Sheet 18 - 33: COMET Blocks These 16 sheets show the connections for the COMET device. Sheet 34: Loopback Test Jig This sheet is not necessary as part of this design. It was used to create a test jig to interface to the Line Card.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
27
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ZONE REV DESCRIPTION DATE APPR
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PAGE 9 FRONT_PANEL TXTIP_F<15..0> TXRING_F<15..0>
PAGES 10-17 LINE_INTERFACE TXTIP<15..0> TXRING<15..0> TVREF<15..0> RXTIP<15..0> RXRING<15..0>
PAGES 18-33 COMET_BLOCK LRXD<15..0> LRXC<15..0> LTXD<15..0> LTXC<15..0> SUNI_DUPLEX_BLOCK
PAGES 2, 3 CPCI_INTERFACE
PAGES 4, 5
TXTIP_F<15..0> G TXRING_F<15..0>
TXTIP_F<15..0>
TXTIP<15..0>
TXTIP<15..0> TXRING<15..0> TVREF<15..0>
LRXD<15..0> LRXC<15..0> LTXD<15..0> LTXC<15..0>
LRXD<15..0> LRXC<15..0>
RXD1P_B RXD1N_B
RXD1P_B RXD1N_B RXD2P_B RXD2N_B TXD1P_B TXD1N_B TXD2P_B TXD2N_B
RXD1P_B RXD1N_B RXD2P_B RXD2N_B TXD1P_B TXD1N_B TXD2P_B TXD2N_B
G
TXRING_F<15..0> TXRING<15..0> TVREF<15..0>
LTXD<15..0> LTXC<15..0> RXD2P_B RXD2N_B TXD1P_B TXD1N_B TXD2P_B TXD2N_B
RXTIP_F<15..0> RXRING_F<15..0>
RXTIP_F<15..0> RXRING_F<15..0>
RXTIP_F<15..0>
RXTIP<15..0>
RXTIP<15..0> RXRING<15..0>
RXRING_F<15..0> RXRING<15..0>
F RSTB_POWER COMET_IRQB<15..0> COMET_CSB<15..0> A_COMETA<8..0> A_COMETB<8..0> D_COMETA<7..0> D_COMETB<7..0> LOOPBACK_CARD RESETB CPU_STAT RSYNC<15..0> TDO_COMET15
F
TDO_FPGA
TCLKI_A
TCLKI_B
RESETB
XCLK_B
XCLK_A
TRSTB
RDB
WRB
TMS
TCK
DUPLEX_IRQB
TDO_COMET15
DUPLEX_CSB
E D<7..0> A<7..0>
TDO_DUPLEX
E TRSTB RSTOB TX8K RX8K
RDB
WRB
TMS
COMET_IRQB<15..0> DUPLEX_IRQB
D
TCK
PAGE 6 MICRO_BLOCK A_M<23..0> D_M<15..0> ASB DSB R/WB SIZ1 SIZ0 RESETB A_M<23..0> D_M<15..0> ASB DSB R/WB SIZ1 SIZ0 RESETB
PAGES 7, 8 MICRO_INTERFACE D<7..0> A<7..0> A_COMETA<8..0> D_M<15..0> A_COMETB<8..0> D_COMETA<7..0> D_COMETB<7..0> ASB DSB RDB R/WB WRB SIZ1 SIZ0 DUPLEX_CSB COMET_CSB<15..0> XCLK_B XCLK_A RSYNC<15..0> TCLKI_A TCLKI_B A_M<23..0> TX8K RX8K CS3B CS2B CS1B CS0B TRSTB MICRO_TDO TMS TCK TDO_FPGA D<7..0> A<7..0> A_COMETA<8..0> A_COMETB<8..0> D_COMETA<7..0> D_COMETB<7..0> RDB WRB DUPLEX_CSB COMET_CSB<15..0> XCLK_B XCLK_A RSYNC<15..0> TCLKI_A TCLKI_B TX8K RX8K TDO_FPGA
D
C
COMET_IRQB<15..0> DUPLEX_IRQB CS3B CS2B CS1B CS0B TRSTB MICRO_TDO TDO_DUPLEX TMS TCK RSTOB RSTB_POWER CPU_STAT
C
CS3B CS2B CS1B CS0B TRSTB MICRO_TDO TDO_DUPLEX TMS TCK RSTOB RSTB_POWER B CPU_STAT
B
PMC-Sierra, Inc.
NOTE: ALL TRACES ARE 75 OHMS UNLESS OTHERWISE NOTED A DRAWING TITLE=DSLAM_LC_ROOT ABBREV=DSLAM_LC_ROOT LAST_MODIFIED=Wed Aug 18 15:58:29 1999 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD ROOT DRAWING ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE: 1.0 DATE: 99/07/27 PAGE:1 TRUE 1 OF 33 A
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NOTE: VCC = +5V NOTE: VDD_A = +3.3V
ZONE
REV
DESCRIPTION
DATE
APPR
H
H
NOTE: PLACE FILTER NETWORKS AS PHYSICALLY CLOSE TO THE DEVICE AS POSSIBLE. VDD_A 3.3 V PBGA U64
1.0K 20.0 20.0 3.3 R225 R258 R259 R260
VDD<15> VDD<14> VDD<13> VDD<12> VDD<11> VDD<10> VDD<9> VDD<8> VDD<7> VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> VDD<0>
P6 N13 N3 M12 M7 L9 L4 L1 K1 F3 E14 E2 D10 C13 C5 B3
ALTERNATE CAPS ON SUNI-DUPLEX VDD PINS
C45 22UF 0.01UF 22UF 0.01UF 0.01UF C215 0.01UF C217 0.01UF C211 0.01UF C207 0.01UF C176 0.01UF C181 0.01UF 0.1UF C216 0.1UF C214 0.1UF C208 0.1UF C206 0.1UF C178 0.1UF 0.1UF C210 0.1UF 22UF 0.01UF 22UF 0.01UF C213 0.01UF C179 C212 C209
G VCC
A7 L13 L14 4.75K G12 H11 H8 H7 G8 G7
G 3.3 V 3.3 V
R21
BIAS ATP1 ATP0 RES RESK GND<3> GND<2> GND<1> GND<0>
S/UNI-DUPLEX PM7350 POWER 4 OF 4 VSS<19> VSS<18> VSS<17> VSS<16> VSS<15> VSS<14> VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> VSS<0>
QAVD QAVS CAVD CAVS RAVD RAVS TAVD<1> TAVD<0> TAVS<1> TAVS<0>
M13 M14 L11 L12 J11 J12 K11 G11 K12 H12
C175 C50 C203 C51 C204 C52 C205
P10 P5 P3 N14 N11 M8 M6 M2 L8 K4 J3 G2 E12 D7 D4 C12 C10 C8 C3 B5
F
F
E
8F3>
PBGA U64 A<7..0>\I 3.3 V
4.7K 4.7K
E
C14 D13 D12 D14 F11 F13 F12 F14 P13 A12 B13 B12 A13 7 6 5 4 3 2 1 0
3.3 V
7 6 5 4 3 2 1 0
8E3> 8E3> 8E3> 6F10<
RDB\I WRB\I DUPLEX_CSB\I DUPLEX_IRQB\I
1
C9 A9 B9 B10 D11 A11 C11 B11 A8 D9 D8 B8 B7 A10
A<7> D<7> A<6> D<6> A<5> D<5> A<4> D<4> A<3> D<3> A<2> D<2> A<1> D<1> A<0>PM7350 D<0> RDB MICRO WRB JTAG TDO CSB 1 OF 4 TDI TCK ALE TMS INTB RSTB TRSTB S/UNI-DUPLEX
D<7..0>\I
8D3<>
R22
R28
TDO_DUPLEX\I TDO_COMET15\I TCK\I TMS\I TRSTB\I
6D8< 33D2> 6E10> 6E10> 6D10>
D
SW2 DUPLEX RESET
2
PBNO
C48 0.1UF
D
PBGA U64
32E10< 31E10< 30E10< 26E10< 25F10< 24F10< 20F10< 19E10< 18E10< 23F10< 22F10< 21F10< 29F10< 28F10< 27E10< 33E10<
LTXD<15..0>\I
C
32E10< 31E10< 30E10< 26E10< 25E10< 24E10< 20E10< 19E10< 18E10< 23E10< 22E10< 21E10< 29E10< 28F10< 27E10< 33E10<
LTXC<15..0>\I
B
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RN12 RN12 RN13 RN14 RN14 RN11 RN10 RN13 RN11 RN10 RN9 RN7 RN8 RN8 RN9 RN7 RN12 RN12 RN14 RN14 RN11 RN11 RN13 RN10 RN10 RN13 RN9 RN8 RN8 RN7 RN9 RN7
2 4 1 4 1 4 3 4 2 2 4 3 1 4 3 1 3 1 3 2 3 1 3 4 1 2 1 3 2 2 2 4
7 5 8 5 8 5 6 5 7 7 5 6 8 5 6 8 6 8 6 7 6 8 6 5 8 7 8 6 7 7 7 5
56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56
A6 C6 B2 C2 D1 F2 G1 G4 G3 H2 J1 P4 N1 M5 M11 N12 B6 D5 B1 C1 E1 F1 F4 H3 H1 H4 L3 M3 N2 P7 M10 N10
S/UNI-DUPLEX LTXD<15> LRXD<15> LTXD<14> LRXD<14> LTXD<13> LRXD<13> LTXD<12> LRXD<12> LTXD<11> LRXD<11> LTXD<10> LRXD<10> LTXD<9> LRXD<9> LTXD<8> LRXD<8> LTXD<7> LRXD<7> LTXD<6> LRXD<6> LTXD<5> LRXD<5> LTXD<4> LRXD<4> LTXD<3> LRXD<3> LTXD<2> LRXD<2> LTXD<1> LRXD<1> LTXD<0> LRXD<0> LTXC<15> LRXC<15> LTXC<14> LRXC<14> LTXC<13> LRXC<13> LTXC<12> LRXC<12> LTXC<11> LRXC<11> LTXC<10> LRXC<10> LTXC<9> LRXC<9> LTXC<8> LRXC<8> LTXC<7> LRXC<7> LTXC<6> LRXC<6> LTXC<5> LRXC<5> LTXC<4> LRXC<4> LTXC<3> LRXC<3> LTXC<2> LRXC<2> LTXC<1> LRXC<1> LTXC<0> LRXC<0> PM7350 SCIANY SERIAL LINE 2 OF 4
D6 A4 B4 D2 E3 J2 K3 L2 P2 M4 N6 L6 L7 P9 M9 L10 A5 C4 A3 D3 E4 J4 K2 M1 N4 L5 N5 N7 P8 N8 N9 P11 C7
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LRXD<15..0>\I
30E10> 31E10> 32E10> 18E10> 19E10> 20E10> 21E10> 22E10> 23E10> 24E10> 25E10> 26E10> 27E10> 28E10> 29E10> 33E10>
C
LRXC<15..0>\I
32E10> 33E10> 18E10> 19E10> 20E10> 21E10> 22E10> 23E10> 24E10> 25E10> 26E10> 27E10> 28E10> 29E10> 30E10> 31E10>
B
PMC-Sierra, Inc.
A DRAWING TITLE=SUNI_DUPLEX_BLOCK ABBREV=SUNI_DUPLEX_BLOCK LAST_MODIFIED=Thu Sep 16 13:46:57 1999 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD S/UNI-DUPLEX BLOCK 1 ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE: 1 DATE: 99/07/27 PAGE:2 1 OF 33 A
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ZONE
NOTE: VCC = +5V
REV
DESCRIPTION
DATE
APPR
H NOTE: INSTALL EITHER TRANSFORMER T5 OR CAPACITORS C408-C415 AND RESISTORS R237-R244
C71 0.22UF C72 0.22UF 1.00M R94
H
T5
39
50 OHM
TXP
TDP
2
50 OHM
G 50 OHM MOUNT ON FRONT PANEL
2MM J4 P1 P2 P3 P4 P5 P6
MH1 MH2 MH3 1.00M 37 4
G 50 OHM
TXN
R93
TDN
3 0.1UF 7 0.1UF C92
1 2 3 4 5 6 MH1 MH2 MH3
H1026
34
J11 BP RXD1P FP
C91 3 2
H3
1.00M
F
MOLEX 53460-0611
NOTE: PLACE R4, R5, AND C416 CLOSE TO S/UNI-DUPLEX. 3.3 V F
49.9 750 C180 10UF 0.1UF C43 430 R229 R228 R23 R24
50 OHM
R92
50 OHM
35
RXP
RDP
6
50 OHM J12 BP RXD1N FP
3 2
H3
1
50 OHM
49.9
3.3 V
50 OHM
1.00M R91
33
8
50 OHM
J9
C69 0.22UF C70 0.22UF
H3
1
E
5E3> 5C9> 5F3< 5F9< 5E3> 5C9> 5F3< 5F9<
BP TXD1P FP 50 50 50 50 50 50 50 50 OHM OHM OHM OHM OHM OHM OHM OHM
PBGA U64
1 R27 4.7K
RXN
RDN
3 R29 4.7K A2 E11 E13 B14 P12
TP19 T U15_RCLK
3.3 V
1
2
D4 1N5820 RSTOB\I RX8K\I TX8K\I
2
50 OHM
G14 G13 H14 H13 J14 J13 K14 K13
R226
49.9
R25
750
RXD1P_B\I RXD1N_B\I TXD1P_B\I TXD1N_B\I RXD2P_B\I RXD2N_B\I TXD2P_B\I TXD2N_B\I
J10 BP TXD1N FP
3 2
H3
50 OHM
S/UNI-DUPLEX RXD1+ RXD1RSTOB TXD1+ RCLK TXD1RX8K RXD2+ TX8K RXD2REFCLK TXD2+ TXD2PM7350 LVDS 3 OF 4
C49 0.1UF
6B8< 8E10< 8E3>
E
1
J15
3
Y4
56 R265 8
VCC
1
BP RXD2P FP
3.3 V
2
50 OHM
H3
OSC_TTL OUT 5V GND 25.0000MHZ 100 PPM
14 7 C229 0.01UF C228 0.1UF
C177
10UF
R26
D
C67 0.22UF
C44 430
J16
3
0.1UF
49.9
R227
H3
BP RXD2N FP
D
2 1
50 OHM
C68 0.22UF 1.00M
J13 T5
29
H3
BP TXD2P FP
12
R90
3
NOTE: PLACE R90, R87, AND C172 CLOSE TO S/UNI-DUPLEX.
2 1
50 OHM
50 OHM
TXP
TDP
50 OHM
H3
BP TXD2N FP 50 OHM
R89 27 14
3
J14
2
50 OHM
50 OHM
TXN
TDN
C MOUNT ON FRONT PANEL
2MM J28 P1 P2 P3 P4 P5 P6
MH1 MH2 MH3
1.00M
1
C
13 0.1UF 17 0.1UF C89 C90
1 2 3 4 5 6 MH1 MH2 MH3
H1026
24
1.00M
MOLEX 53460-0611
B 50 OHM
25
R88
B
RXP RDP
16
50 OHM
50 OHM
1.00M
23
18
50 OHM
RXN
R87
RDN
C65 0.22UF C66 0.22UF
PMC-Sierra, Inc.
DRAWING TITLE=SUNI_DUPLEX_BLOCK ABBREV=SUNI_DUPLEX_BLOCK LAST_MODIFIED=Thu Sep 16 13:46:59 1999 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD S/UNI-DUPLEX BLOCK 2 ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE: 1 DATE: 99/07/27 PAGE:3 1 OF 33 A
A
10
9
8
7
6
5
4
3
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE
NOTE: VCC = +5V H H
REV
DESCRIPTION
DATE
APPR
G
VCC
3.3 V
VCC
MOUNT LED ON FRONT PANEL LGD D3
G
6G2>
+5V_OK +3.3V_OK CPU_STAT\I
R12 R11 R10 R9
270 100 270 270
A1 A2 A3 A4
K1 K2 K3 K4
RESETB\I
6B10>
INSTALL EITHER R126 (IF AVAILABLE), OR R114-R119, R122-R125. D5
1 .01 0.1UF C59 4.7UF 2
LED SSF-LXH5147
J1
F
E
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 F1 F3 F5 F7 F9 F11 F13 F15 F17 F19 F21 F23 F25
C60
.10 .10 .10 .10 .10 .10 .10 .10 .10 .10
1N5817M F
0.1UF
R267 R266 R269 R268 R270 R37 R41 R42 R43 R45 R44
Q2 SOIC
8 7 6 5
DI9410
TO-220_HORZ U68 LT1585
1000UF 10UF 3 2 1 3 C62
NOTE: VDD_A = 3.3V ANALOG VDD_A
2 C64 0 R30 47UF C53 1UF C54
C56
VIN
VOUT
0.1UF
R38 8 7 6
C63
4
10
1
GND
VOUT_TAB
4
VCC
SENSE
GATE
R40 2.43K R39
U67
0 R33 0.1UF C55
4.7K R36
2
ON
TIMER
FB LTC1422 SOIC RESET GND
5
6.81K
E RSTB_POWER\I
6A10<
1
4.7K
R35
0.33UF
3
3
4.7K R34
0 R31
1 2
MMBT3904
C61
4
3.3 V
VCC D
C38 22UF
D
0 R32
22UF
C39 22UF
C36 22UF
C37 22UF
C41 22UF
22UF
C46 22UF
C3 22UF
C40 22UF
C47
C
E1 F1 E2 F3 E3 F5 F7 E4 F9 E5 F11 E6 F13 E7 F15 E8 F17 E9 F19 E10 F21 E11 F23 E15 F25 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 ZPACK5X22A 2MM CPCI
0.1UF
C58
4.7UF
C57
C42
3.3 V TP8 T +3.3V TP23 T +3.3V TP18 T +3.3V TP15 T +3.3V VCC
VCC TP25 T +5V TP3 T +5V TP16 T +5V TP10 T +5V
TP24 T GND TP4 T GND TP21 T GND TP17 T GND TP5 T GND TP22 T GND C
PLACE CORRECT SIZE MOUNTING HOLE P4
P1
1 2 3
TP14 T GND TP26 T GND TP11 T GND B
STRIP3 B STRIP2
1
10M 2 R98
HOLE_SIZE= 150 MIL
MOUNTING HOLE
PWRBLOCK_2
NOTE: TERMINAL BLOCK USED TO SUPPLY POWER IF NO CPCI CONNECTOR EXISTS
10M R97
STRIP1
CPCI ESD STRIP
1
TP1 T CHASSIS TP6 T CHASSIS
10M
R264
PMC-Sierra, Inc.
DRAWING A TITLE=CPCI_INTERFACE ABBREV=CPCI_INTERFACE LAST_MODIFIED=Thu Sep 16 13:47:03 1999 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD CPCI INTERFACE ENGINEER: 10 9 8 7 6 5 4 3 PMC-SIERRA, INC. (WT) 2 ISSUE: 1 DATE: 99/07/27 PAGE:4 1 OF 33 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
NOTE: VCC = +5V
ZONE
REV
DESCRIPTION
DATE
APPR
H
H
R52
100 100 100 100 100 100
G
3.3 V
R58 R64 R70 R76 R82
3.3 V
G
J5
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22
R46 R50 R56
200 1.0K 1.0K 1.0K 1.0K
F
R62 R68
3E10> 3D10>
TXD1N_B\I TXD2N_B\I
R78 R80 1.0K 1.0K
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22
R48 R54 R60 R66 R72
200 2.0K 2.0K 2.0K 2.0K
F
TXD1P_B\I TXD2P_B\I
R74 R83 2.0K 2.0K
3E10> 3D10>
E
R47 R53 R59 R65
2.0K 2.0K 2.0K 2.0K
E
RXD1P_B\I RXD2P_B\I
R71 R77 2.0K 2.0K
3E10< 3E10<
D
R51 R57 R63 R69 1.0K 1.0K 1.0K 1.0K
3E10< 3E10<
RXD1N_B\I RXD2N_B\I
R75 R81 1.0K 1.0K
C
E1 F2 E2 E3 F4 E4 E5 F6 E6 E7 F8 E8 E9 F10 E10 E11 F12 E12 E13 E14 F14 E15 F16 E16 E17 F18 E18 E19 F20 E20 E21 F22 E22 ZPACK5X22B 2MM CPCI
D
C
R49 R55 R61 R67 R73 R79
100 100 100 100 100 100
B
B
PMC-Sierra, Inc.
A DRAWING TITLE=CPCI_INTERFACE ABBREV=CPCI_INTERFACE LAST_MODIFIED=Thu Sep 16 13:47:05 1999 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD LVDS INTERFACE ENGINEER: 10 9 8 7 6 5 4 3 PMC-SIERRA, INC. (WT) 2 ISSUE: 1 DATE: 99/07/27 PAGE:5 1 OF 33 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
VCC
ZONE
C174 0.1UF C79 0.1UF C171 0.1UF C98 0.1UF C96 0.1UF C172 0.1UF C170 0.1UF
REV
DESCRIPTION
DATE
APPR
H MOUNT ON FRONT PANEL SERIAL PORT J2 12 23 34 45 56 67 78 8 RJ45
1 14 7 13 8 1 3
VCC U1 T1O T2O R1I T1I T2I R1O
11 10 12 9 4 5 2 16 15 C86 0.1UF
H
TXD1 RTS1 RXD1 CTS1
C82 0.1UF C85 0.1UF C83 0.1UF
VCC
C84 0.1UF
C97 0.1UF
C1 0.1UF
C88 0.1UF
C173 0.1UF
C100 0.1UF
C102 0.1UF
C101 0.1UF
C2 10UF
C87 0.1UF
R2I R2O MAX202 C2+ C1+ C1C2V+ VVCC GND
C81 0.1UF 19
VCC DECOUPLING CAPS FOR 68340 PLACE DECOUPLING CAPS CLOSE TO THE POWER PINS Y3
8 1
15 17 23 35 41 50 59 68 78 90 102 113 123 134 143
VCC
14 7 C231 0.01UF C230 0.1UF
VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15
VCC
C80 0.1UF 6
G
31D10> 30D10> 27D10> 26D10> 23D10> 22D10> 19D10> 18D10> 21D10> 20D10> 25D10> 24D10> 29D10> 28D10> 33D10> 32D10>
COMET_IRQB<15..0>\I
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
77 80 76 81 83 82 85 84 86
VCCSYN
56 R271
TXD1 RTS1B/OP0 RXD1 CTS1B TXRDY1B RXRDY1B TXD2 RXD2 RTS2B/OP1 CTS2B SCLK
OUT NC/CV
5V GND
G
X1 X2 IACK7B/A31/A.7 IACK6B/A30/A.6 IACK5B/A29/A.5 IACK4B/A28/A.4 IACK3B/A27/A.3 IACK2B/A26/A.2 IACK1B/A25/A.1 IACK0B/A24/A.0 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 FC3 FC2 FC1 FC0 ASB DSB R/WB SIZ1 SIZ0 HALTB BRB BGB BGACKB RMCB
92 89 139 138 137 136 133 132 131 130 43 44 45 46 47 48 49 52 53 54 56 57 58 61 62 63 64 65 66 67 70 71 72 140 129 128 127 125 122 121 120 119 118 117 116 115 112 111 110 109 37 38 39 40 6 5 2 3 4 11
3.6864MHZ CPU_STAT\I LID D2
A1 A2 A3 A4 K1 K2 K3 K4
4G3<
VCC RN5
4 3 2 1
VCC 4.7K
5 6 7 8
4.7K R223
87 88
RN4
4 3 2 1
4.7K
5 6 7 8 99 100 101
R8 R7 R6 R5 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
270 270 270 270
LOS1 LCD1 LOS2 LCD2
LED SSF-LXH5147
MOUNT ON FRONT PANEL
F
8F10< 2D8> 8F10< 8F10< 8F10< 7D10<
IRQ7B/B.7 IRQ6B/B.6 IRQ5B/B.5 CS3B/IRQ4B/B.4 IRQ3B/B.3 CS2B/IRQ2B/B.2 CS1B/IRQ1B/B.1 MODCK/B.0 CS0B/AVECB TIN1 TOUT1
F
CS3B\I DUPLEX_IRQB\I CS2B\I CS1B\I CS0B\I
104 105 106 107 22 108 28 29
VCC RN3
4 2 3 1
4.7K
5 7 6 8 30 73 75 74 34 33 32 31
TGATE1B TGATE2B TIN2 TOUT2 TDO TDI TMS TCK DREQ1B DACK1B DONE1B DREQ2B DACK2B DONE2B CLKOUT XTAL EXTAL XFC
A_M<23..0>\I
7G10< 8D10< 8G10<
E
8B10< 30D1< 31D1<24D2< 21D2< 20D2< 22D2< 27D1<32D1<23D2< 2D4< 33D2< 25D2<26D2<8B10< 18D2< 28D2<29D1<19D1< 25D2<19D1< 18D2< 28D2< 30D1< 31D1< 22D2< 24D2<23D2< 29D1<27D1< 26D2< 2D4< 21D2< 32D1<33D2< 20D2< 8B10< 33D2< 30D1< 29D1< 26D2< 25D2< 22D2< 21D2< 18D2< 2D4< 20D2< 19D1< 24D2< 23D2< 28D2< 27D1< 32D1< 31D1<
MICRO_TDO\I TMS\I TCK\I VCC VCC
R273 4.7K 4.7K R272 4.7K R150 4.7K R151
U36 MC68340FE25
E
TP2 T CLKOUT
VCC RN6
1 2 3 4
4.7K
8 7 6 5
U65
12
F08
TRSTB\I J27
1 2 3 4 5 6
11 13
93 94 95 96 97 98 14
D_M<15..0>\I
7C10<> 8F10<>
D
P_1 P_2 P_3 JTAG PORT P_4 P_5 P_6
HDR6
VCC
14 C222 0.1UF C225 0.01UF
Y2 5V GND OUT NC/CV
8 1
20 56 R262 18
TDO_DUPLEX\I
VCC
16
2D4>
7
25.0000MHZ
C99 0.1UF
ASB\I DSB\I R/WB\I SIZ1\I SIZ0\I VCC
8G10< 6D2> 8G10< 7B10< 8G10< 8G10< 8G10<
D
RN1
9 8 7 1 1 2 3 4
4.7K
8 7 6 5
12
RSTB
VCC J3 C
1 3 5 7 9 10 2 4 6 8 10
DSACK1B BERRB DSACK0B VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 BKPTB/DSCLK FREEZE IFETCHB/DSI IPIPEB/DSO
142 141 4.7K R149
P_1 P_2 P_3 P_4 P_5 P_6 P_7 P_8 P_9 P_10
HEADER 5X2
BERRB BKPTB FREEZE IFETCHB IPIPEB
26 27 25 24
C
VCC RN2
33D10< 30D10< 29D10< 26D10< 25D10< 22D10< 21D10< 18D10< 4G1< 20D10< 19D10< 24D10< 23D10< 28D10< 27D10< 32D10< 31D10<
1 3 2 4
4.7K
8 6 7 5
RESETB\I
8G10< 6D2>
DSB\I B
B
U65 VCC
C232 0.1UF
VCC
8
F08
9 10
RSTOB\I
3E2>
13 21 36 42 51 55 60 69 79 91 103 114 124 126 135 144
1 2 3 4
8 7 6 5 4 1
PRELIMINARY - SUBJECT TO CHANGE WITHOUT NOTICE
U65
6 1 3 2
F08
U65
5
RN15 SW1 4.7K
C227 0.1UF
PBNO
F08
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-990354 DRAWING TITLE=MICRO_BLOCK ABBREV=MICRO_BLOCK LAST_MODIFIED=Thu Sep 16 13:46:45 1999 TITLE: DSLAM LINE CARD MICROPROCESSOR BLOCK ENGINEER: 3 PMC-SIERRA, INC. (WT) 2 PAGE:6 TRUE 1 OF 33 ISSUE: 1.0 DATE: 99/07/27 A
2
BDM_RSTB A
RESET CIRCUIT
4E3>
RSTB_POWER\I
10
9
8
7
6
5
4
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
6E2>
A_M<23..0>\I
G
23 22 21 20 19 18 17 16
2 3 4 5 6 7 8 9
U62 A0 A1 A2 A3 A4 A5 A6 A7
U2 B0 B1 B2 B3 B4 B5 B6 B7
18 17 16 15 14 13 12 11 19 1 23 22 21 20 19 18 17 16
A_I<23..0>
VCC
C190 0.1UF
20 10
VCC GOE* GND DIR 74FCT245 U44 A0 A1 A2 A3 A4 A5 A6 A7
VCC
F
15 14 13 12 11 10 9 8
2 3 4 5 6 7 8 9
B0 B1 B2 B3 B4 B5 B6 B7
18 17 16 15 14 13 12 11 19 1
15 14 13 12 11 10 9 8
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 R96 4.7K
35 34 33 32 24 23 22 21 20 18 17 16 15 14 5 4 3 2 1 6 13 31
A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CS WE OE 25NS
IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0
30 29 26 25 12 11 8 7
7 6 5 4 3 2 1 0
G
VCC VCC VCC
9 27 C76 0.1UF C78 0.1UF C77 10UF
GND GND
10 28
CY7C1049 512KX8 SRAM
F
VCC
C168 0.1UF
20 10
VCC GOE* GND DIR 74FCT245 U43 A0 A1 A2 A3 A4 A5 A6 A7
VCC
U3
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 R95 4.7K 35 34 33 32 24 23 22 21 20 18 17 16 15 14 5 4 3 2 1 6 13 31
E
7 6 5 4 3 2 1 0
2 3 4 5 6 7 8 9
B0 B1 B2 B3 B4 B5 B6 B7
18 17 16 15 14 13 12 11 19 1
7 6 5 4 3 2 1 0
VCC
C167 0.1UF
20 10
VCC GOE* GND DIR 74FCT245
VCC
A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CS WE OE 25NS
IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0
30 29 26 25 12 11 8 7
15 14 13 12 11 10 9 8
E
VCC VCC VCC
9 27 C73 0.1UF C75 0.1UF C74 10UF
GND GND
10 28
CY7C1049 512KX8 SRAM
VCC D PLCC U37
AT27C4096 100NS
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 25 24 34
D
C94 0.1UF 44 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C93 0.1UF C95 10UF
8D10> 8D10> 8D10> 6F10>
LWEB UWEB OEB CS0B\I PI74FCT16245T U42
8F10<> 6D2<>
D_M<15..0>\I
C
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
6D2>
R/WB\I
1 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 24 4 10 15 21 28 34
DIR 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 DIR GND GND GND GND GND GND
OE* 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 OE* VCC VCC VCC VCC GND GND
48 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 25 7 18 31 42 45 39
DEB_MEM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
8D10>
VPP
A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 GND
2
VCC O15 O14 O13 O12 O11 O10 O9 O8 O7 O6 O5 O4 O3 O2 O1 O0 GND
3 22
C
VCC
VCC B D_I<15..0>
B
C169 0.1UF
CE OE
PRELIMINARY - SUBJECT TO CHANGE WITHOUT NOTICE
PMC-Sierra, Inc.
A DRAWING TITLE=MICRO_INTERFACE ABBREV=MICRO_INTERFACE LAST_MODIFIED=Thu Sep 16 13:46:47 1999 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD MICROPROCESSOR INTERFACE 1 ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE: 1.0 DATE: 99/07/27 PAGE:7 TRUE 1 OF 33 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
VCC
3.3 V
U61
183 136 133 130 79 32 29 17 2 202 182 164 132 98 80 60 28 106
VCCA<9> VCCA<8> VCCA<7> VCCA<6> VCCA<5> VCCA<4> VCCA<3> VCCA<2> VCCA<1> VCCI<8> VCCI<7> VCCI<6> VCCI<5> VCCI<4> VCCI<3> VCCI<2> VCCI<1>
VCC
G
6E2> 6D2> 6D2> 6D2> 6D2> 6D2> 6F10> 6F10> 6F10> 6F10> 7C10<> 6D2<>
G
26 25 24 23 21 20 19 18 16 15 14 13 12 11 10 9 8 7 6 5 4 208 206 205 204 203 201 200 199 198 197 195 194 193 192 191 190 189 187 185 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
A_M<23..0>\I R/WB\I ASB\I DSB\I SIZ0\I SIZ1\I CS3B\I CS2B\I CS1B\I CS0B\I D_M<15..0>\I
21 22 23
F
33E2> 25E2>24E2>23E2>22E2>21E2>20E2>19E1>18E2> 32E1>31E1>30E1>29E1>28E2>27E1>26E2>
RSYNC<15..0>\I
8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R222 R221 R220 33 1.0K 33
E
3E2>
RX8K\I 8KHZ PORT P_1 P_2 J18 P_3 P_4 HEADER4
1 2 3 4
J26
1 3 5 7 9 11 13 15
VCC
10K R263 2
FPGA EXPANSION PORT
1
P_1 P_3 P_5 P_7 P_9 P_11 P_13 P_15
P_2 P_4 P_6 P_8 P_10 P_12 P_14 P_16
2 4 6 8 10 12 14 16
TP9 T FPGA3
77 76 75 74 73 72 71 70 69 68 67 66 64 63 62 61 59 58 57 56 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 31 30 127 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 104 102 101 100 99 97 96 95 94 93 92 90 89 88 87 86 85 84 83 82 81 65 91 3 207 159 178 188 54 55 103 128
IO_A<41> IO_A<40> IO_A<39> IO_A<38> IO_A<37> IO_A<36> IO_A<35> IO_A<34> IO_A<33> IO_A<32> IO_A<31> IO_A<30> IO_A<29> IO_A<28> IO_A<27> IO_A<26> IO_A<25> IO_A<24> IO_A<23> IO_A<22> IO_A<21> IO_A<20> IO_A<19> IO_A<18> IO_A<17> IO_A<16> IO_A<15> IO_A<14> IO_A<13> IO_A<12> IO_A<11> IO_A<10> IO_A<9> IO_A<8> IO_A<7> IO_A<6> IO_A<5> IO_A<4> IO_A<3> IO_A<2> IO_A<1> IO_B<41> IO_B<40> IO_B<39> IO_B<38> IO_B<37> IO_B<36> IO_B<35> IO_B<34> IO_B<33> IO_B<32> IO_B<31> IO_B<30> IO_B<29> IO_B<28> IO_B<27> IO_B<26> IO_B<25> IO_B<24> IO_B<23> IO_B<22> IO_B<21> IO_B<20> IO_B<19> IO_B<18> IO_B<17> IO_B<16> IO_B<15> IO_B<14> IO_B<13> IO_B<12> IO_B<11> IO_B<10> IO_B<9> IO_B<8> IO_B<7> IO_B<6> IO_B<5> IO_B<4> IO_B<3> IO_B<2> IO_B<1> QCLKA_IO QCLKB_IO MODE DCLK_IO SDI_IO PRA_IO PRB_IO TMS_IO TDI_IO TDO_IO TCK_IO
IO_C<40> IO_C<39> IO_C<38> IO_C<37> IO_C<36> IO_C<35> IO_C<34> IO_C<33> IO_C<32> IO_C<31> IO_C<30> IO_C<29> IO_C<28> IO_C<27> IO_C<26> IO_C<25> IO_C<24> IO_C<23> IO_C<22> IO_C<21> IO_C<20> IO_C<19> IO_C<18> IO_C<17> IO_C<16> IO_C<15> IO_C<14> IO_C<13> IO_C<12> IO_C<11> IO_C<10> IO_C<9> IO_C<8> IO_C<7> IO_C<6> IO_C<5> IO_C<4> IO_C<3> IO_C<2> IO_C<1>
A_COMETA<8..0>\I
18D10< 19D10< 20E10< 21E10< 22E10< 23E10< 24E10< 25E10<
A_COMETB<8..0>\I
26D10< 27D10< 28E10< 29E10< 30D10< 31D10< 32D10< 33D10<
A<7..0>\I
F
2E8<
D_COMETA<7..0>\I
18E10<> 19E10<> 20E10<> 21E10<> 22E10<> 23E10<> 24E10<> 25E10<>
56 56
HEADER 8X2 FPGA4 T TP20
J25 ROM/BDM SELECT D
7D10< 7D10< 7D10< 7C7< 6E2>
LWEB UWEB OEB DEB_MEM A_M<23..0>\I
C VCC
2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
IO_D<40> IO_D<39> IO_D<38> IO_D<37> IO_D<36> IO_D<35> IO_D<34> IO_D<33> IO_D<32> IO_D<31> IO_D<30> IO_D<29> IO_D<28> IO_D<27> IO_D<26> IO_D<25> IO_D<24> IO_D<23> IO_D<22> IO_D<21> IO_D<20> IO_D<19> IO_D<18> IO_D<17> IO_D<16> IO_D<15> IO_D<14> IO_D<13> IO_D<12> IO_D<11> IO_D<10> IO_D<9> IO_D<8> IO_D<7> IO_D<6> IO_D<5> IO_D<4> IO_D<3> IO_D<2> IO_D<1> QCLKC_IO QCLKD_IO CLKA_IO CLKB_IO GND_<1> GND_<2> GND_<3> GND_<4> GND_<5> GND_<6> GND_<7> GND_<8> GND_<9> GND_<10> GND_<11> GND_<12> GND_<13>
181 179 177 176 175 174 173 172 170 169 168 167 166 165 163 162 161 160 158 156 155 154 153 152 151 149 148 147 146 145 144 143 142 141 140 139 138 137 135 134 196 171 180 186
R4 R3 R2 R1
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T FPGA1 LID D1 MOUNT ON FRONT PANEL 100 K1 A1 COMG1 100 K2 A2 COMG2 100 K3 A3 COMG3 100 K4 A4 COMG4 LED TP13 FPGA2 T SSF-LXH5147 TCLKI_A\I R256 56 TCLKI_B\I R257 56 D_COMETB<7..0>\I
R254 R255
WRB\I RDB\I DUPLEX_CSB\I TX8K\I XCLK_A\I XCLK_B\I TP12
2D8< 18D10< 19D10< 20D10< 21D10< 22D10< 23D10< 24D10< 25D10< 26D10< 27D10< 28D10< 29D10< 30D10< 31D10< 32D10< 33D10< 23D10< 24D10< 25D10< 26D10< 27D10< 2E8< 18D10< 19D10< 20D10< 21D10< 22D10< 28D10< 29D10< 30D10< 31D10< 32D10< 33D10< 2D8< 3E2< 18E2< 19D1< 20E2< 21E2< 22E2< 23E2< 24E2< 25E2< 26E2< 27E1< 28E2< 29E1< 30E1< 31E1< 32E1< 33E2<
E
18E2< 19E1< 20E2< 21E2< 22E2< 23E2< 24E2< 25E2< 26E2< 27E1< 28E2< 29E1< 30E1< 31E1< 32E1< 33E2< 26E10<> 27E10<> 28E10<> 29E10<> 30E10<> 31E10<> 32E10<> 33E10<>
D D<7..0>\I
2E3<>
COMET_CSB<15..0>\I
18D10< 19D10< 20D10< 21D10< 22D10< 23D10< 24D10< 25D10< 26D10< 27D10< 28D10< 29D10< 30D10< 31D10< 32D10< 33D10<
C
Y1
56 R261 8
J19
10K R219
1
OSC_TTL OUT 5V GND 2.048MHZ 50 PPM
VCC
14 7 C218 0.01UF C219 0.1UF
A42MX36_PQ208
B
6E10> 6E10> 18D2< 6E10>
TMS\I MICRO_TDO\I TDO_FPGA\I TCK\I J23 P_1 P_2 P_3 P_4 FPGA TEST PORT P_5
HEADER5
1 2 3 4 5
B
1 22 27 52 53 78 105 126 129 131 150 157 184
VCC
0.1UF 0.1UF C220 0.1UF C198 0.1UF C200 0.1UF C195 0.1UF C192 0.1UF C221 0.1UF C226 0.1UF 0.1UF C202 0.1UF C199 0.1UF C194 0.1UF C201 0.1UF C223 0.1UF C196 0.1UF C193 0.1UF
3.3 V
NOTE: COMG1 COMG2 COMG3 COMG4
= = = =
COMETS COMETS COMETS COMETS
1-4 5-8 9-12 13-16
PRELIMINARY - SUBJECT TO CHANGE WITHOUT NOTICE
PMC-Sierra, Inc.
C191
C197
A DRAWING DECOUPLING CAPS FOR FPGA. PLACE ONE PER PIN. TITLE=MICRO_INTERFACE ABBREV=MICRO_INTERFACE LAST_MODIFIED=Thu Sep 16 13:46:52 1999 6 5 4 3
C224
DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD MICROPROCESSOR INTERFACE 2 ENGINEER: PMC-SIERRA, INC. (WT) 2
ISSUE: 1.0 DATE: 99/07/27 PAGE:8 TRUE 1 OF 33
A
10
9
8
7
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
16F2<16C2< 17F2< 15F2<15C2<14F2<14C2< 13F2<13C2<12F2<12C2< 17C2< 11F2<11C2<10F2<10C2< 17E2< 17B2< 13B2<12E2<12B2<11E2<11B2<10E2<10B2< 16E2<16B2<15E2<15B2<14E2<14B2<13E2<
A1 C1
GND=CHASSIS_ 71626-4000 P2 A1 B1 B1 C1 D1 D1 A2 C2 A3 C3 A4 C4 A5 C5 A6 C6 A7 C7 A8 C8 A9 C9 A10 C10 A11 C11 A12 C12 A13 C13 A14 C14 A15 C15 A16 C16 A17 C17 A18 C18 A19 C19 A20 C20 A21 C21 A22 C22 A23 C23 A24 C24 A25 C25 A26 C26 A27 C27 A28 C28 A29 C29 A30 C30 A31 C31 A32 C32 A33 C33 A34 C34 A35 C35 A36 C36 A37 C37 A38 C38 A39 C39 A40 C40 B2 D2 B3 D3 B4 D4 B5 D5 B6 D6 B7 D7 B8 D8 B9 D9 B10 D10 B11 D11 B12 D12 B13 D13 B14 D14 B15 D15 B16 D16 B17 D17 B18 D18 B19 D19 B20 D20 B21 D21 B22 D22 B23 D23 B24 D24 B25 D25 B26 D26 B27 D27 B28 D28 B29 D29 B30 D30 B31 D31 B32 D32 B33 D33 B34 D34 B35 D35 B36 D36 B37 D37 B38 D38 B39 D39 B40 D40
B2 D2 B3 D3 B4 D4 B5 D5 B6 D6 B7 D7 B8 D8 B9 D9 B10 D10 B11 D11 B12 D12 B13 D13 B14 D14 B15 D15 B16 D16 B17 D17 B18 D18 B19 D19 B20 D20 B21 D21 B22 D22 B23 D23 B24 D24
0 0
TXTIP_F<15..0>\I TXRING_F<15..0>\I
10D2> 10G2> 11D2> 11G2> 12D2> 12G2> 13D2> 13G2> 14D2> 14G2> 15D2> 15G2> 16D2> 16G2> 10C2> 10G2> 11C2> 11G2> 12C2> 12G2> 13C2> 13G2> 17D2> 17G2> 14C2> 14G2> 15C2> 15G2> 16C2> 16G2> 17C2> 17G2>
RXTIP_F<15..0>\I RXRING_F<15..0>\I
0 0
A2 C2 A3 C3
1 1
1 1
A4 C4 A5 C5 A6 C6
G
G
2 2
2 2
A7 C7 A8 C8
3 3
3 3
A9 C9 A10 C10
F
4 4
A11 C11 A12 C12 A13 C13 5 5 A14 C14 A15 C15 A16 C16 6 6 A17 C17 A18 C18 7 7 A19 C19 A20 C20 A21 C21 8 8 A22 C22 A23 C23 9 9 A24 C24 A25 C25 A26 C26 10 10 A27 C27 A28 C28 11 11 A29 C29 A30 C30
4 4
F
5 5
6 6
E
7 7
E
8 8
9 9
D
B25 D25 B26 D26 B27 D27 B28 D28 B29 D29 B30 D30 B31 D31 B32 D32 B33 D33 B34 D34 B35 D35 B36 D36 B37 D37 B38 D38 B39 D39 B40 D40 15 15 14 14 13 13 12 12 11 11 10 10
D
C
12 12
A31 C31 A32 C32 A33 C33 13 13 A34 C34 A35 C35 A36 C36 14 14 A37 C37 A38 C38 15 15 A39 C39 A40 C40
C
B
B
PRELIMINARY - SUBJECT TO CHANGE WITHOUT NOTICE
PMC-Sierra, Inc.
A DRAWING TITLE=FRONT_PANEL ABBREV=FRONT_PANEL LAST_MODIFIED=Thu Sep 16 13:46:54 1999 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD FRONT PANEL ENGINEER: PMC-SIERRA, INC. (WT) 2 PAGE:9 TRUE 1 OF 33 ISSUE: 1.0 DATE: 99/07/27 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
TXTIP_F<0>\I
1
9H4<
LC03_6
18E2>
U4
LINE1A LINE2A
TXTIP<0>\I
12.7 R148
G
18D2<
U38
4.7UF C4 1
T9021
1:2.42
40
2 3
LINE2B LINE1B
8
SOIC
GND1 GND2
GND3 GND4
6 7
G
TVREF<0>\I
12.7 R147
18E2>
TXRING<0>\I
3
38
TXRING_F<0>\I
4
5
9H4<
3.3 V
2
RXTIP_F<0>\I
1
9G8>
LC03_6
F
7 2
U5
LINE1A LINE2A
LINE2B LINE1B
8
SOIC
F GND3 GND4
6 7
GND1 GND2
18E2<
RXTIP<0>\I
18.2 R146 4
3
1:2.42
37
18E2<
RXRING<0>\I
5
36
RXRING_F<0>\I
4
5
9G8>
E E
D
19E1>
D TXTIP<1>\I
12.7 R145 6
1:2.42
35 1
TXTIP_F<1>\I
9H4<
LC03_6
4.7UF 8 33 2 3
U7
LINE1A LINE2A
19D1<
TVREF<1>\I
12.7 R144
LINE2B LINE1B
8
SOIC
C6
GND1 GND2
GND3 GND4
6 7
19E1>
TXRING<1>\I
4
C
5
TXRING_F<1>\I
9H4<
C
19E1<
RXTIP<1>\I
18.2 R143
9
1:2.42
32 1
RXTIP_F<1>\I
9G8>
LC03_6
10 31 2 3
U6
LINE1A LINE2A
19E1<
RXRING<1>\I GND1 GND2
LINE2B LINE1B
8
SOIC
GND3 GND4
6 7
RXRING_F<1>\I
4
5
9G8>
B
B
100K R100
TP7 T
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-990354 DRAWING TITLE=LINE_INTERFACE ABBREV=LINE LAST_MODIFIED=Thu Sep 16 13:46:13 1999 TITLE: DSLAM LINE CARD LINE INTERFACE 1 ENGINEER: 3 PMC-SIERRA, INC. (WT) 2 ISSUE: 1.0 DATE: 99/07/27 PAGE:10 TRUE 1 OF 33 A
A
10
9
8
7
6
5
4
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
TXTIP_F<2>\I
1
9H4<
LC03_6
20F2>
U9
LINE1A LINE2A
TXTIP<2>\I
12.7 R142
G
20E2<
U38
4.7UF C8 11
T9021
1:2.42
30
2 3
LINE2B LINE1B
8
SOIC
GND1 GND2
GND3 GND4
6 7
G
TVREF<2>\I
12.7 R141
20F2>
TXRING<2>\I
13
28
TXRING_F<2>\I
4
5
9H4<
3.3 V
12
RXTIP_F<2>\I
1
9G8>
LC03_6
F
17 2
U8
LINE1A LINE2A
LINE2B LINE1B
8
SOIC
F GND3 GND4
6 7
GND1 GND2
20E2<
RXTIP<2>\I
18.2 R140 14
3
1:2.42
27
20E2<
RXRING<2>\I
15
26
RXRING_F<2>\I
4
5
9G8>
E E
D
21F2>
D TXTIP<3>\I
12.7 R139 16
1:2.42
25 1
TXTIP_F<3>\I
9H4<
LC03_6
4.7UF 18 23 2 3
U11
LINE1A LINE2A
21E2<
TVREF<3>\I
12.7 R138
LINE2B LINE1B
8
SOIC
C10
GND1 GND2
GND3 GND4
6 7
21F2>
TXRING<3>\I
4
C
5
TXRING_F<3>\I
9H4<
C
21E2<
RXTIP<3>\I
18.2 R137
19
1:2.42
22 1
RXTIP_F<3>\I
9G8>
LC03_6
20 21 2 3
U10
LINE1A LINE2A
21E2<
RXRING<3>\I GND1 GND2
LINE2B LINE1B
8
SOIC
GND3 GND4
6 7
RXRING_F<3>\I
4
5
9G8>
B
B
PMC-Sierra, Inc.
A DRAWING TITLE=LINE_INTERFACE ABBREV=LINE LAST_MODIFIED=Thu Sep 16 13:46:14 1999 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD LINE INTERFACE 2 ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE: 1.0 DATE: 99/07/27 PAGE:11 TRUE 1 OF 33 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
TXTIP_F<4>\I
1
9H4<
LC03_6
22F2>
U13
LINE1A LINE2A
TXTIP<4>\I
12.7 R136
G
22E2<
U39
4.7UF C12 1
T9021
1:2.42
40
2 3
LINE2B LINE1B
8
SOIC
GND1 GND2
GND3 GND4
6 7
G
TVREF<4>\I
12.7 R135
22F2>
TXRING<4>\I
3
38
TXRING_F<4>\I
4
5
9H4<
3.3 V
2
RXTIP_F<4>\I
1
9G8>
LC03_6
F
7 2
U12
LINE1A LINE2A
LINE2B LINE1B
8
SOIC
F GND3 GND4
6 7
GND1 GND2
22E2<
RXTIP<4>\I
18.2 R134 4
3
1:2.42
37
22E2<
RXRING<4>\I
5
36
RXRING_F<4>\I
4
5
9G8>
E E
D
23F2>
D TXTIP<5>\I
12.7 R133 6
1:2.42
35 1
TXTIP_F<5>\I
9H4<
LC03_6
4.7UF 8 33 2 3
U15
LINE1A LINE2A
23E2<
TVREF<5>\I
12.7 R132
LINE2B LINE1B
8
SOIC
C14
GND1 GND2
GND3 GND4
6 7
23F2>
TXRING<5>\I
4
C
5
TXRING_F<5>\I
9H4<
C
23E2<
RXTIP<5>\I
18.2 R131
9
1:2.42
32 1
RXTIP_F<5>\I
9G8>
LC03_6
10 31 2 3
U14
LINE1A LINE2A
23E2<
RXRING<5>\I GND1 GND2
LINE2B LINE1B
8
SOIC
GND3 GND4
6 7
4
B
5
RXRING_F<5>\I
9G8>
B
PMC-Sierra, Inc.
A DRAWING TITLE=LINE_INTERFACE ABBREV=LINE LAST_MODIFIED=Thu Sep 16 13:46:15 1999 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD LINE INTERFACE 3 ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE: 1.0 DATE: 99/07/27 PAGE:12 TRUE 1 OF 33 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
TXTIP_F<6>\I
1
9H4<
LC03_6
24F2>
U17
LINE1A LINE2A
TXTIP<6>\I
12.7 R130
G
24E2<
U39
4.7UF C16 11
T9021
1:2.42
30
2 3
LINE2B LINE1B
8
SOIC
GND1 GND2
GND3 GND4
6 7
G
TVREF<6>\I
12.7 R129
24F2>
TXRING<6>\I
13
28
TXRING_F<6>\I
4
5
9H4<
3.3 V
12
RXTIP_F<6>\I
1
9G8>
LC03_6
F
17 2
U16
LINE1A LINE2A
LINE2B LINE1B
8
SOIC
F GND3 GND4
6 7
GND1 GND2
24E2<
RXTIP<6>\I
18.2 R128 14
3
1:2.42
27
24E2<
RXRING<6>\I
15
26
RXRING_F<6>\I
4
5
9G8>
E E
D
25F2>
D TXTIP<7>\I
12.7 R127 16
1:2.42
25 1
TXTIP_F<7>\I
9H4<
LC03_6
4.7UF 18 23 2 3
U19
LINE1A LINE2A
25E2<
TVREF<7>\I
12.7 R126
LINE2B LINE1B
8
SOIC
C17
GND1 GND2
GND3 GND4
6 7
25F2>
TXRING<7>\I
4
C
5
TXRING_F<7>\I
9H4<
C
25E2<
RXTIP<7>\I
18.2 R125
19
1:2.42
22 1
RXTIP_F<7>\I
9G8>
LC03_6
20 21 2 3
U18
LINE1A LINE2A
25E2<
RXRING<7>\I GND1 GND2
LINE2B LINE1B
8
SOIC
GND3 GND4
6 7
RXRING_F<7>\I
4
5
9G8>
B
B
PMC-Sierra, Inc.
A DRAWING TITLE=LINE_INTERFACE ABBREV=LINE LAST_MODIFIED=Thu Sep 16 13:46:16 1999 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD LINE INTERFACE 4 ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE: 1.0 DATE: 99/07/27 PAGE:13 TRUE 1 OF 33 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
TXTIP_F<8>\I
1
9H4<
LC03_6
26E2>
U21
LINE1A LINE2A
TXTIP<8>\I
12.7 R124
G
26D2<
U40
4.7UF C20 1
T9021
1:2.42
40
2 3
LINE2B LINE1B
8
SOIC
GND1 GND2
GND3 GND4
6 7
G
TVREF<8>\I
12.7 R123
26E2>
TXRING<8>\I
3
38
TXRING_F<8>\I
4
5
9H4<
3.3 V
2
RXTIP_F<8>\I
1
9G8>
LC03_6
F
7 2
U20
LINE1A LINE2A
LINE2B LINE1B
8
SOIC
F GND3 GND4
6 7
GND1 GND2
26E2<
RXTIP<8>\I
18.2 R122 4
3
1:2.42
37
26E2<
RXRING<8>\I
5
36
RXRING_F<8>\I
4
5
9G8>
E E
D
27E1>
D TXTIP<9>\I
12.7 R121 6
1:2.42
35 1
TXTIP_F<9>\I
9H4<
LC03_6
4.7UF 8 33 2 3
U23
LINE1A LINE2A
27D1<
TVREF<9>\I
12.7 R120
LINE2B LINE1B
8
SOIC
C21
GND1 GND2
GND3 GND4
6 7
27E1>
TXRING<9>\I
4
C
5
TXRING_F<9>\I
9H4<
C
27E1<
RXTIP<9>\I
18.2 R119
9
1:2.42
32 1
RXTIP_F<9>\I
9G8>
LC03_6
10 31 2 3
U22
LINE1A LINE2A
27E1<
RXRING<9>\I GND1 GND2
LINE2B LINE1B
8
SOIC
GND3 GND4
6 7
RXRING_F<9>\I
4
5
9G8>
B
B
PMC-Sierra, Inc.
A DRAWING TITLE=LINE_INTERFACE ABBREV=LINE LAST_MODIFIED=Thu Sep 16 13:46:17 1999 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD LINE INTERFACE 5 ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE: 1.0 DATE: 99/07/27 PAGE:14 TRUE 1 OF 33 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
TXTIP_F<10>\I
1
9H4<
LC03_6
28F2>
U25
LINE1A LINE2A
TXTIP<10>\I
12.7 R118
G
28E2<
U40
4.7UF C24 11
T9021
1:2.42
30
2 3
LINE2B LINE1B
8
SOIC
GND1 GND2
GND3 GND4
6 7
G
TVREF<10>\I
12.7 R117
28F2>
TXRING<10>\I
13
28
TXRING_F<10>\I
4
5
9H4<
3.3 V
12
RXTIP_F<10>\I
1
9G8>
LC03_6
F
17 2
U24
LINE1A LINE2A
LINE2B LINE1B
8
SOIC
F GND3 GND4
6 7
GND1 GND2
28E2<
RXTIP<10>\I
18.2 R116 14
3
1:2.42
27
28E2<
RXRING<10>\I
15
26
RXRING_F<10>\I
4
5
9G8>
E E
D
29F1>
D TXTIP<11>\I
12.7 R115 16
1:2.42
25 1
TXTIP_F<11>\I
9H4<
LC03_6
4.7UF 18 23 2 3
U27
LINE1A LINE2A
29E1<
TVREF<11>\I
12.7 R114
LINE2B LINE1B
8
SOIC
C25
GND1 GND2
GND3 GND4
6 7
29E1>
TXRING<11>\I
4
C
5
TXRING_F<11>\I
9H4<
C
29E1<
RXTIP<11>\I
18.2 R113
19
1:2.42
22 1
RXTIP_F<11>\I
9G8>
LC03_6
20 21 2 3
U26
LINE1A LINE2A
29E1<
RXRING<11>\I GND1 GND2
LINE2B LINE1B
8
SOIC
GND3 GND4
6 7
RXRING_F<11>\I
4
5
9G8>
B
B
PMC-Sierra, Inc.
A DRAWING TITLE=LINE_INTERFACE ABBREV=LINE LAST_MODIFIED=Thu Sep 16 13:46:19 1999 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD LINE INTERFACE 6 ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE: 1.0 DATE: 99/07/27 PAGE:15 TRUE 1 OF 33 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
TXTIP_F<12>\I
1
9H4<
LC03_6
30E1>
U29
LINE1A LINE2A
TXTIP<12>\I
12.7 R112
G
30D1<
U41
4.7UF C28 1
T9021
1:2.42
40
2 3
LINE2B LINE1B
8
SOIC
GND1 GND2
GND3 GND4
6 7
G
TVREF<12>\I
12.7 R111
30E1>
TXRING<12>\I
3
38
TXRING_F<12>\I
4
5
9H4<
3.3 V
2
RXTIP_F<12>\I
1
9G8>
LC03_6
F
7 2
U28
LINE1A LINE2A
LINE2B LINE1B
8
SOIC
F GND3 GND4
6 7
GND1 GND2
30E1<
RXTIP<12>\I
18.2 R110 4
3
1:2.42
37
30E1<
RXRING<12>\I
5
36
RXRING_F<12>\I
4
5
9G8>
E E
D
31E1>
D TXTIP<13>\I
12.7 R109 6
1:2.42
35 1
TXTIP_F<13>\I
9H4<
LC03_6
4.7UF 8 33 2 3
U31
LINE1A LINE2A
31E1<
TVREF<13>\I
12.7 R108
LINE2B LINE1B
8
SOIC
C29
GND1 GND2
GND3 GND4
6 7
31E1>
TXRING<13>\I
4
C
5
TXRING_F<13>\I
9H4<
C
31E1<
RXTIP<13>\I
18.2 R107
9
1:2.42
32 1
RXTIP_F<13>\I
9G8>
LC03_6
10 31 2 3
U30
LINE1A LINE2A
31E1<
RXRING<13>\I GND1 GND2
LINE2B LINE1B
8
SOIC
GND3 GND4
6 7
RXRING_F<13>\I
4
5
9G8>
B
B
PMC-Sierra, Inc.
A DRAWING TITLE=LINE_INTERFACE ABBREV=LINE LAST_MODIFIED=Thu Sep 16 13:46:20 1999 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD LINE INTERFACE 7 ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE: 1.0 DATE: 99/07/27 PAGE:16 TRUE 1 OF 33 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
TXTIP_F<14>\I
1
9H4<
LC03_6
32E1>
U33
LINE1A LINE2A
TXTIP<14>\I
12.7 R106
G
32E1<
U41
4.7UF C32 11
T9021
1:2.42
30
2 3
LINE2B LINE1B
8
SOIC
GND1 GND2
GND3 GND4
6 7
G
TVREF<14>\I
12.7 R105
32E1>
TXRING<14>\I
13
28
TXRING_F<14>\I
4
5
9H4<
3.3 V
12
RXTIP_F<14>\I
1
9G8>
LC03_6
F
17 2
U32
LINE1A LINE2A
LINE2B LINE1B
8
SOIC
F GND3 GND4
6 7
GND1 GND2
32E1<
RXTIP<14>\I
18.2 R104 14
3
1:2.42
27
32E1<
RXRING<14>\I
15
26
RXRING_F<14>\I
4
5
9G8>
E E
D
33E2>
D TXTIP<15>\I
12.7 R103 16
1:2.42
25 1
TXTIP_F<15>\I
9H4<
LC03_6
4.7UF 18 23 2 3
U35
LINE1A LINE2A
33E2<
TVREF<15>\I
12.7 R102
LINE2B LINE1B
8
SOIC
C33
GND1 GND2
GND3 GND4
6 7
33E2>
TXRING<15>\I
4
C
5
TXRING_F<15>\I
9H4<
C
33E2<
RXTIP<15>\I
18.2 R101
19
1:2.42
22 1
RXTIP_F<15>\I
9G8>
LC03_6
20 21 2 3
U34
LINE1A LINE2A
33E2<
RXRING<15>\I GND1 GND2
LINE2B LINE1B
8
SOIC
GND3 GND4
6 7
RXRING_F<15>\I
4
5
9G8>
B
B
PMC-Sierra, Inc.
A DRAWING TITLE=LINE_INTERFACE ABBREV=LINE LAST_MODIFIED=Thu Sep 16 13:46:21 1999 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD LINE INTERFACE 8 ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE: 1.0 DATE: 99/07/27 PAGE:17 TRUE 1 OF 33 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET RAVD PINS 3.3 V
2.2 R214 1UF C164
COMET_1_2_RAVD
19F7<
G 3.3 V
.47
G
COMET_1_2_TAVD 22UF + 3.3 V
1.0 0.01UF R212 C163
19F7<
R13
NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET TAVD PINS 3.3 V
C7
C5 68UF
+
F
3.3 V
F2 F8 D2 E6 G4 A1 B4 B5 A5 A9 A7 A6 G8
VCC
F
U45
TAVD1 TAVD2 TAVD3 TAVD4 RAVD1 RAVD2 QAVD BIAS
VDDI1 VDDI2 VDDO1 VDDO2 VDDO3
2C9> 2B9>
LTXD<0>\I LTXC<0>\I LRXD<0>\I LRXC<0>\I D_COMETA<7..0>\I
56 56 R216 R218
E4 E1 E3 D3 F6 E9 F7 D8 H3 J4 H4 F4 G5 F5 H6 J7 J6 H5 H7 J8 G6 J9 H8 G7 H9 J2 G3 G9 J3 H2 J1
BTFP BTPCM BTSIG BTCLK BRFP BRPCM BRSIG BRCLK D<0> D<1> D<2> D<3> D<4> D<5> D<6> D<7> A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> WRB RDB ALE INTB RSTB CSB VSSI1 VSSI2 VSSO1 VSSO2 VSSO3 TAVS1 TAVS2 TAVS3 TAVS4 RAVS1 RAVS2 QAVS
E
2C4< 2B4< 22E10<> 21E10<> 20E10<> 19E10<> 8F3<> 25E10<> 24E10<> 23E10<>
TXTIP1 TXTIP2 TXRING1 TXRING2 TDAT TFP RXTIP RXRING RDAT RCLKI PM4351 COMET TCLKO RSYNC TCLKI XCLK ATB TVREF RVREF TRIMF NC
D5 A2 C5 C4 C2 D1 C7 A8 E8 D9 C1 C9 B1 C3 B6 A4 D7 C8 B9
TXTIP<0>\I TXRING<0>\I
10G10< 10G10<
RXTIP<0>\I RXRING<0>\I
10F10> 10E10>
E
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8
RSYNC<0>\I TCLKI_A\I XCLK_A\I TVREF<0>\I
0.01UF R217 100K C166
8F10< 8D3> 8E3> 10G10>
8G3>
A_COMETA<8..0>\I VCC
D
8E3> 8E3> 6G10< 6B10> 8D3>
WRB\I RDB\I COMET_IRQB<0>\I RESETB\I COMET_CSB<0>\I
TMS TDI TDO TRSTB TCK
E2 G2 H1 F3 F1
TMS\I TDO_FPGA\I TDO0 TRSTB\I TCK\I
6E10> 8B10> 19D1< 6D10> 6E10>
4.7K
R215
D
G1 F9
D4 E7 J5
B2 A3 B3 C6
B8 B7
C
D6
C
3.3 V
0.01UF
3.3 V
0.1UF
B
C160
C161
B
PLACE CAP ON THE VDDI PIN OF THE COMET
PLACE CAP ON THE VDDO PIN OF THE COMET
PMC-Sierra, Inc.
A DRAWING TITLE=COMET_BLOCK ABBREV=COMET_BLOCK LAST_MODIFIED=Thu Sep 16 13:46:22 1999 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD COMET BLOCK 1 ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE: 1.0 DATE: 99/07/27 PAGE:18 TRUE 1 OF 33 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
G
NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET RAVD PINS
18G5> 18G5>
3.3 V COMET_1_2_RAVD
1.0 0.01UF
COMET_1_2_TAVD
R213 C162
NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET TAVD PINS 3.3 V F 3.3 V
F2 F8 D2 E6 G4 A1 B4 B5 A5 A9 A7 A6 G8
F VCC
U46
TAVD1 TAVD2 TAVD3 TAVD4 RAVD1 RAVD2 QAVD BIAS
VDDI1 VDDI2 VDDO1 VDDO2 VDDO3
2C9>
LTXD<1>\I LTXC<1>\I LRXD<1>\I LRXC<1>\I D_COMETA<7..0>\I
56 56 R252 R211
E
2B9> 2C4< 2B4< 22E10<> 21E10<> 20E10<> 18E10<> 8F3<> 25E10<> 24E10<> 23E10<>
E4 E1 E3 D3 F6 E9 F7 D8 H3 J4 H4 F4 G5 F5 H6 J7 J6 H5 H7 J8 G6 J9 H8 G7 H9 J2 G3 G9 J3 H2 J1
BTFP BTPCM BTSIG BTCLK BRFP BRPCM BRSIG BRCLK D<0> D<1> D<2> D<3> D<4> D<5> D<6> D<7> A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> WRB RDB ALE INTB RSTB CSB VSSI1 VSSI2 VSSO1 VSSO2 VSSO3 TAVS1 TAVS2 TAVS3 TAVS4 RAVS1 RAVS2 QAVS
TXTIP1 TXTIP2 TXRING1 TXRING2 TDAT TFP RXTIP RXRING RDAT RCLKI PM4351 COMET TCLKO RSYNC TCLKI XCLK ATB TVREF RVREF TRIMF NC TMS TDI TDO TRSTB TCK
D5 A2 C5 C4 C2 D1 C7 A8 E8 D9 C1 C9 B1 C3 B6 A4 D7 C8 B9
TXTIP<1>\I TXRING<1>\I
10D10< 10C10<
E RXTIP<1>\I RXRING<1>\I
10C10> 10C10>
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8
RSYNC<1>\I TCLKI_A\I XCLK_A\I TVREF<1>\I
0.01UF R251 100K C159
8F10< 8D3> 8E3> 10D10>
8G3>
A_COMETA<8..0>\I VCC
D
4.7K R253
E2 G2 H1 F3 F1
TMS\I TDO0 TDO1 TRSTB\I TCK\I
8E3> 8E3> 6G10< 6B10> 8D3>
WRB\I RDB\I COMET_IRQB<1>\I RESETB\I COMET_CSB<1>\I
6E10> 18D2> 20D2< 6D10> 6E10>
D
G1 F9
D4 E7 J5
B2 A3 B3 C6
B8 B7
C
D6
C
3.3 V
3.3 V
0.01UF
0.1UF
B
C189
C165
B
PLACE CAP ON THE VDDI PIN OF THE COMET
PLACE CAP ON THE VDDO PIN OF THE COMET
PMC-Sierra, Inc.
A DRAWING TITLE=COMET_BLOCK ABBREV=COMET_BLOCK LAST_MODIFIED=Thu Sep 16 13:46:23 1999 TITLE: DSLAM LINE CARD COMET BLOCK 2 ENGINEER: 10 9 8 7 6 5 4 3 PMC-SIERRA, INC. (WT) 2 DATE: 99/07/27 PAGE:19 1 OF 33 DOCUMENT NUMBER: PMC-990354 ISSUE: 1.0 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET RAVD PINS 3.3 V
2.2 R206 1UF C156
COMET_3_4_RAVD
21G7<
3.3 V G NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET TAVD PINS 3.3 V
.47 R14
COMET_3_4_TAVD 22UF + 3.3 V
1.0 R204 0.01UF C155
21G7<
G
C11
C9 68UF
+
3.3 V
F2 F8 D2 E6 G4 A1 B4 B5 A5 A9 A7 A6 G8
VCC
F
U47
F
TAVD1 TAVD2 TAVD3 TAVD4 RAVD1 RAVD2 QAVD BIAS
VDDI1 VDDI2 VDDO1 VDDO2 VDDO3
2C9> 2B9> 2C4< 2B4<
LTXD<2>\I LTXC<2>\I LRXD<2>\I LRXC<2>\I D_COMETA<7..0>\I
56 56 R208 R210
E4 E1 E3 D3 F6 E9 F7 D8 H3 J4 H4 F4 G5 F5 H6 J7 J6 H5 H7 J8 G6 J9 H8 G7 H9 J2 G3 G9 J3 H2 J1
BTFP BTPCM BTSIG BTCLK BRFP BRPCM BRSIG BRCLK D<0> D<1> D<2> D<3> D<4> D<5> D<6> D<7> A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> WRB RDB ALE INTB RSTB CSB VSSI1 VSSI2 VSSO1 VSSO2 VSSO3 TAVS1 TAVS2 TAVS3 TAVS4 RAVS1 RAVS2 QAVS
TXTIP1 TXTIP2 TXRING1 TXRING2 TDAT TFP RXTIP RXRING RDAT RCLKI PM4351 COMET TCLKO RSYNC TCLKI XCLK ATB TVREF RVREF TRIMF NC TMS TDI TDO TRSTB TCK
D5 A2 C5 C4 C2 D1 C7 A8 E8 D9 C1 C9 B1 C3 B6 A4 D7 C8 B9
TXTIP<2>\I TXRING<2>\I
11G10< 11G10<
RXTIP<2>\I RXRING<2>\I
11F10> 11E10>
E
24E10<> 22E10<> 19E10<> 8F3<> 18E10<> 21E10<> 23E10<> 25E10<>
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8
E RSYNC<2>\I TCLKI_A\I XCLK_A\I TVREF<2>\I
0.01UF R209 100K C158
8F10< 8D3> 8E3> 11G10>
8G3>
A_COMETA<8..0>\I VCC
E2 G2 H1 F3 F1
TMS\I TDO1 TDO2 TRSTB\I TCK\I
8E3> 8E3>
WRB\I RDB\I COMET_IRQB<2>\I RESETB\I COMET_CSB<2>\I
6E10> 19D1> 21D2< 6D10> 6E10>
D
4.7K
R207
6G10< 6B10> 8D3>
D
G1 F9
D4 E7 J5
B2 A3 B3 C6
B8 B7
C
D6
C
3.3 V
0.01UF
3.3 V
0.1UF
B
PLACE CAP ON THE VDDI PIN OF THE COMET
C153
PLACE CAP ON THE VDDO PIN OF THE COMET
C152
B
PMC-Sierra, Inc.
A DRAWING TITLE=COMET_BLOCK ABBREV=COMET_BLOCK LAST_MODIFIED=Thu Sep 16 13:46:25 1999 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD COMET BLOCK 3 ENGINEER: 10 9 8 7 6 5 4 3 PMC-SIERRA, INC. (WT) 2 ISSUE: 1.0 DATE: 99/07/27 PAGE:20 1 OF 33 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET RAVD PINS
20H5> 20G5>
G 3.3 V COMET_3_4_RAVD
1.0 0.01UF
COMET_3_4_TAVD 3.3 V
R205 C154
NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET TAVD PINS
3.3 V
F2 F8 D2 E6 G4 A1 B4 B5 A5 A9 A7 A6 G8
VCC
F
U48
F
TAVD1 TAVD2 TAVD3 TAVD4 RAVD1 RAVD2 QAVD BIAS
VDDI1 VDDI2 VDDO1 VDDO2 VDDO3
2C9> 2B9> 2C4< 2B4<
LTXD<3>\I LTXC<3>\I LRXD<3>\I LRXC<3>\I D_COMETA<7..0>\I
56 56 R249 R203
E4 E1 E3 D3 F6 E9 F7 D8 H3 J4 H4 F4 G5 F5 H6 J7 J6 H5 H7 J8 G6 J9 H8 G7 H9 J2 G3 G9 J3 H2 J1
BTFP BTPCM BTSIG BTCLK BRFP BRPCM BRSIG BRCLK D<0> D<1> D<2> D<3> D<4> D<5> D<6> D<7> A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> WRB RDB ALE INTB RSTB CSB VSSI1 VSSI2 VSSO1 VSSO2 VSSO3 TAVS1 TAVS2 TAVS3 TAVS4 RAVS1 RAVS2 QAVS
TXTIP1 TXTIP2 TXRING1 TXRING2 TDAT TFP RXTIP RXRING RDAT RCLKI PM4351 COMET TCLKO RSYNC TCLKI XCLK ATB TVREF RVREF TRIMF NC TMS TDI TDO TRSTB TCK
D5 A2 C5 C4 C2 D1 C7 A8 E8 D9 C1 C9 B1 C3 B6 A4 D7 C8 B9
TXTIP<3>\I TXRING<3>\I
11D10< 11C10<
RXTIP<3>\I RXRING<3>\I
11C10> 11C10>
E
24E10<> 22E10<> 19E10<> 8F3<> 18E10<> 20E10<> 23E10<> 25E10<>
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8
E RSYNC<3>\I TCLKI_A\I XCLK_A\I TVREF<3>\I
0.01UF R248 100K C151
8F10< 8D3> 8E3> 11D10>
8G3>
A_COMETA<8..0>\I VCC
4.7K R250
E2 G2 H1 F3 F1
TMS\I TDO2 TDO3 TRSTB\I TCK\I
D
8E3> 8E3> 6G10< 6B10> 8D3>
WRB\I RDB\I COMET_IRQB<3>\I RESETB\I COMET_CSB<3>\I
6E10> 20D2> 22D2< 6D10> 6E10>
D
G1 F9
D4 E7 J5
B2 A3 B3 C6
B8 B7
C
D6
C
3.3 V
0.01UF
3.3 V
0.1UF
B
PLACE CAP ON THE VDDI PIN OF THE COMET
C188
PLACE CAP ON THE VDDO PIN OF THE COMET
C157
B
PMC-Sierra, Inc.
A DRAWING TITLE=COMET_BLOCK ABBREV=COMET_BLOCK LAST_MODIFIED=Thu Sep 16 13:46:26 1999 TITLE: DSLAM LINE CARD COMET BLOCK 4 ENGINEER: 10 9 8 7 6 5 4 3 PMC-SIERRA, INC. (WT) 2 DATE: 99/07/27 PAGE:21 1 OF 33 DOCUMENT NUMBER: PMC-990354 ISSUE: 1.0 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET RAVD PINS 3.3 V
2.2 C148 R198 1UF
H
COMET_5_6_RAVD
23G7<
3.3 V G NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET TAVD PINS 3.3 V
.47 R15
COMET_5_6_TAVD 22UF +
23G7<
G
3.3 V
1.0 R196 0.01UF C147
C15
C13 68UF
+
3.3 V
F2 F8 D2 E6 G4 A1 B4 B5 A5 A9 A7 A6 G8
VCC
F
U49
F
TAVD1 TAVD2 TAVD3 TAVD4 RAVD1 RAVD2 QAVD BIAS
VDDI1 VDDI2 VDDO1 VDDO2 VDDO3
2C9> 2B9> 2C4< 2B4<
LTXD<4>\I LTXC<4>\I LRXD<4>\I LRXC<4>\I D_COMETA<7..0>\I
56 56 R200 R202
E4 E1 E3 D3 F6 E9 F7 D8 H3 J4 H4 F4 G5 F5 H6 J7 J6 H5 H7 J8 G6 J9 H8 G7 H9 J2 G3 G9 J3 H2 J1
BTFP BTPCM BTSIG BTCLK BRFP BRPCM BRSIG BRCLK D<0> D<1> D<2> D<3> D<4> D<5> D<6> D<7> A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> WRB RDB ALE INTB RSTB CSB VSSI1 VSSI2 VSSO1 VSSO2 VSSO3 TAVS1 TAVS2 TAVS3 TAVS4 RAVS1 RAVS2 QAVS
TXTIP1 TXTIP2 TXRING1 TXRING2 TDAT TFP RXTIP RXRING RDAT RCLKI PM4351 COMET TCLKO RSYNC TCLKI XCLK ATB TVREF RVREF TRIMF NC TMS TDI TDO TRSTB TCK
D5 A2 C5 C4 C2 D1 C7 A8 E8 D9 C1 C9 B1 C3 B6 A4 D7 C8 B9
TXTIP<4>\I TXRING<4>\I
12G10< 12G10<
RXTIP<4>\I RXRING<4>\I
12F10> 12E10>
E
24E10<> 21E10<> 19E10<> 8F3<> 18E10<> 20E10<> 23E10<> 25E10<>
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8
E RSYNC<4>\I TCLKI_A\I XCLK_A\I TVREF<4>\I
0.01UF R201 100K C150
8F10< 8D3> 8E3> 12G10>
8G3>
A_COMETA<8..0>\I VCC
4.7K R199
E2 G2 H1 F3 F1
TMS\I TDO3 TDO4 TRSTB\I TCK\I
D
8E3> 8E3> 6G10< 6B10> 8D3>
WRB\I RDB\I COMET_IRQB<4>\I RESETB\I COMET_CSB<4>\I
6E10> 21D2> 23D2< 6D10> 6E10>
D
G1 F9
D4 E7 J5
B2 A3 B3 C6
B8 B7
C
D6
C
3.3 V
0.01UF
3.3 V
0.1UF
B
PLACE CAP ON THE VDDI PIN OF THE COMET
C144
PLACE CAP ON THE VDDO PIN OF THE COMET
C145
B
PMC-Sierra, Inc.
A DRAWING TITLE=COMET_BLOCK ABBREV=COMET_BLOCK LAST_MODIFIED=Thu Sep 16 13:46:27 1999 TITLE: DSLAM LINE CARD COMET BLOCK 5 ENGINEER: 10 9 8 7 6 5 4 3 PMC-SIERRA, INC. (WT) 2 DATE: 99/07/27 PAGE:22 1 OF 33 DOCUMENT NUMBER: PMC-990354 ISSUE: 1.0 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET RAVD PINS
22H5> 22G5>
G 3.3 V COMET_5_6_RAVD
1.0 0.01UF
COMET_5_6_TAVD
R197 C146
NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET TAVD PINS 3.3 V
3.3 V
F2 F8 D2 E6 G4 A1 B4 B5 A5 A9 A7 A6 G8
VCC
F
U50
F
TAVD1 TAVD2 TAVD3 TAVD4 RAVD1 RAVD2 QAVD BIAS
VDDI1 VDDI2 VDDO1 VDDO2 VDDO3
2C9> 2B9> 2C4< 2B4<
LTXD<5>\I LTXC<5>\I LRXD<5>\I LRXC<5>\I D_COMETA<7..0>\I
56 56 R246 R195
E4 E1 E3 D3 F6 E9 F7 D8 H3 J4 H4 F4 G5 F5 H6 J7 J6 H5 H7 J8 G6 J9 H8 G7 H9 J2 G3 G9 J3 H2 J1
BTFP BTPCM BTSIG BTCLK BRFP BRPCM BRSIG BRCLK D<0> D<1> D<2> D<3> D<4> D<5> D<6> D<7> A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> WRB RDB ALE INTB RSTB CSB VSSI1 VSSI2 VSSO1 VSSO2 VSSO3 TAVS1 TAVS2 TAVS3 TAVS4 RAVS1 RAVS2 QAVS
TXTIP1 TXTIP2 TXRING1 TXRING2 TDAT TFP RXTIP RXRING RDAT RCLKI PM4351 COMET TCLKO RSYNC TCLKI XCLK ATB TVREF RVREF TRIMF NC TMS TDI TDO TRSTB TCK
D5 A2 C5 C4 C2 D1 C7 A8 E8 D9 C1 C9 B1 C3 B6 A4 D7 C8 B9
TXTIP<5>\I TXRING<5>\I
12D10< 12C10<
RXTIP<5>\I RXRING<5>\I
12C10> 12C10>
E
24E10<> 21E10<> 19E10<> 8F3<> 18E10<> 20E10<> 22E10<> 25E10<>
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8
E RSYNC<5>\I TCLKI_A\I XCLK_A\I TVREF<5>\I
0.01UF 100K R245 C143
8F10< 8D3> 8E3> 12D10>
8G3>
A_COMETA<8..0>\I VCC
4.7K R247
E2 G2 H1 F3 F1
TMS\I TDO4 TDO5 TRSTB\I TCK\I
8E3> 8E3>
WRB\I RDB\I COMET_IRQB<5>\I RESETB\I COMET_CSB<5>\I
6E10> 22D2> 24D2< 6D10> 6E10>
D
6G10< 6B10> 8D3>
D
G1 F9
D4 E7 J5
B2 A3 B3 C6
B8 B7
C
D6
C
3.3 V
0.01UF
3.3 V
0.1UF
B
PLACE CAP ON THE VDDI PIN OF THE COMET
C187
PLACE CAP ON THE VDDO PIN OF THE COMET
C149
B
PMC-Sierra, Inc.
A DRAWING TITLE=COMET_BLOCK ABBREV=COMET_BLOCK LAST_MODIFIED=Thu Sep 16 13:46:28 1999 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD COMET BLOCK 6 ENGINEER: 10 9 8 7 6 5 4 3 PMC-SIERRA, INC. (WT) 2 ISSUE: 1.0 DATE: 99/07/27 PAGE:23 1 OF 33 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET RAVD PINS 3.3 V
2.2 R190 1UF C140
H
COMET_7_8_RAVD
25G7<
3.3 V G NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET TAVD PINS 3.3 V
.47 R16
COMET_7_8_TAVD 22UF +
1.0 0.01UF R188 C139
25G7<
G
3.3 V
C19
C18 68UF
+
3.3 V
F2 F8 D2 E6 G4 A1 B4 B5 A5 A9 A7 A6 G8
VCC
F
U51
F
TAVD1 TAVD2 TAVD3 TAVD4 RAVD1 RAVD2 QAVD BIAS
VDDI1 VDDI2 VDDO1 VDDO2 VDDO3
2C9> 2B9> 2C4< 2B4<
LTXD<6>\I LTXC<6>\I LRXD<6>\I LRXC<6>\I D_COMETA<7..0>\I
56 56 R192 R194
E4 E1 E3 D3 F6 E9 F7 D8 H3 J4 H4 F4 G5 F5 H6 J7 J6 H5 H7 J8 G6 J9 H8 G7 H9 J2 G3 G9 J3 H2 J1
BTFP BTPCM BTSIG BTCLK BRFP BRPCM BRSIG BRCLK D<0> D<1> D<2> D<3> D<4> D<5> D<6> D<7> A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> WRB RDB ALE INTB RSTB CSB VSSI1 VSSI2 VSSO1 VSSO2 VSSO3 TAVS1 TAVS2 TAVS3 TAVS4 RAVS1 RAVS2 QAVS
TXTIP1 TXTIP2 TXRING1 TXRING2 TDAT TFP RXTIP RXRING RDAT RCLKI PM4351 COMET TCLKO RSYNC TCLKI XCLK ATB TVREF RVREF TRIMF NC TMS TDI TDO TRSTB TCK
D5 A2 C5 C4 C2 D1 C7 A8 E8 D9 C1 C9 B1 C3 B6 A4 D7 C8 B9
TXTIP<6>\I TXRING<6>\I
13G10< 13G10<
RXTIP<6>\I RXRING<6>\I
13F10> 13E10>
E
23E10<> 21E10<> 19E10<> 8F3<> 18E10<> 20E10<> 22E10<> 25E10<>
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8
E RSYNC<6>\I TCLKI_A\I XCLK_A\I TVREF<6>\I
0.01UF R193 100K C142
8F10< 8D3> 8E3> 13G10>
8G3>
A_COMETA<8..0>\I VCC
4.7K R191
E2 G2 H1 F3 F1
TMS\I TDO5 TDO6 TRSTB\I TCK\I
8E3> 8E3>
WRB\I RDB\I COMET_IRQB<6>\I RESETB\I COMET_CSB<6>\I
6E10> 23D2> 25D2< 6D10> 6E10>
D
6G10< 6B10> 8D3>
D
G1 F9
D4 E7 J5
B2 A3 B3 C6
B8 B7
C
D6
C
3.3 V
0.01UF
3.3 V
0.1UF
B
PLACE CAP ON THE VDDI PIN OF THE COMET
C136
PLACE CAP ON THE VDDO PIN OF THE COMET
C137
B
PMC-Sierra, Inc.
A DRAWING TITLE=COMET_BLOCK ABBREV=COMET_BLOCK LAST_MODIFIED=Thu Sep 16 13:46:30 1999 TITLE: DSLAM LINE CARD COMET BLOCK 7 ENGINEER: 10 9 8 7 6 5 4 3 PMC-SIERRA, INC. (WT) 2 DATE: 99/07/27 PAGE:24 1 OF 33 DOCUMENT NUMBER: PMC-990354 ISSUE: 1.0 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET RAVD PINS
24H5> 24G5>
G 3.3 V COMET_7_8_RAVD
1.0 0.01UF
COMET_7_8_TAVD
R189 C138
NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET TAVD PINS 3.3 V
3.3 V
F2 F8 D2 E6 G4 A1 B4 B5 A5 A9 A7 A6 G8
VCC
F
U52
F
TAVD1 TAVD2 TAVD3 TAVD4 RAVD1 RAVD2 QAVD BIAS
VDDI1 VDDI2 VDDO1 VDDO2 VDDO3
2C9> 2B9> 2C4< 2B4<
LTXD<7>\I LTXC<7>\I LRXD<7>\I LRXC<7>\I D_COMETA<7..0>\I
56 56 R243 R187
E4 E1 E3 D3 F6 E9 F7 D8 H3 J4 H4 F4 G5 F5 H6 J7 J6 H5 H7 J8 G6 J9 H8 G7 H9 J2 G3 G9 J3 H2 J1
BTFP BTPCM BTSIG BTCLK BRFP BRPCM BRSIG BRCLK D<0> D<1> D<2> D<3> D<4> D<5> D<6> D<7> A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> WRB RDB ALE INTB RSTB CSB VSSI1 VSSI2 VSSO1 VSSO2 VSSO3 TAVS1 TAVS2 TAVS3 TAVS4 RAVS1 RAVS2 QAVS
TXTIP1 TXTIP2 TXRING1 TXRING2 TDAT TFP RXTIP RXRING RDAT RCLKI PM4351 COMET TCLKO RSYNC TCLKI XCLK ATB TVREF RVREF TRIMF NC TMS TDI TDO TRSTB TCK
D5 A2 C5 C4 C2 D1 C7 A8 E8 D9 C1 C9 B1 C3 B6 A4 D7 C8 B9
TXTIP<7>\I TXRING<7>\I
13D10< 13C10<
RXTIP<7>\I RXRING<7>\I
13C10> 13C10>
E
22E10<> 21E10<> 18E10<> 8F3<> 20E10<> 19E10<> 24E10<> 23E10<>
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8
E RSYNC<7>\I TCLKI_A\I XCLK_A\I TVREF<7>\I
0.01UF R242 100K C135
8F10< 8D3> 8E3> 13D10>
8G3>
A_COMETA<8..0>\I VCC
E2 G2 H1 F3 F1
TMS\I TDO6 TDO7 TRSTB\I TCK\I
D
8E3> 8E3> 6G10< 6B10> 8D3>
WRB\I RDB\I COMET_IRQB<7>\I RESETB\I COMET_CSB<7>\I
6E10> 24D2> 26D2< 6D10> 6E10>
4.7K
R244
D
G1 F9
D4 E7 J5
B2 A3 B3 C6
B8 B7
C
D6
C
3.3 V
3.3 V
0.01UF
0.1UF
B
PLACE CAP ON THE VDDI PIN OF THE COMET
C186
PLACE CAP ON THE VDDO PIN OF THE COMET
C141
B
PMC-Sierra, Inc.
A DRAWING TITLE=COMET_BLOCK ABBREV=COMET_BLOCK LAST_MODIFIED=Thu Sep 16 13:46:31 1999 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD COMET BLOCK 8 ENGINEER: 10 9 8 7 6 5 4 3 PMC-SIERRA, INC. (WT) 2 ISSUE: 1.0 DATE: 99/07/27 PAGE:25 1 OF 33 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET RAVD PINS 3.3 V
2.2 R182 C132
COMET_9_10_RAVD
27G6<
1UF
G 3.3 V
.47
G
COMET_9_10_TAVD +
27G6<
NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET TAVD PINS 3.3 V
R17
C23 22UF
0.01UF C131
3.3 V
1.0 R180
+ C22 68UF F 3.3 V
F2 F8 D2 E6 G4 A1 B4 B5 A5 A9 A7 A6 G8
VCC
F
U53
TAVD1 TAVD2 TAVD3 TAVD4 RAVD1 RAVD2 QAVD BIAS
VDDI1 VDDI2 VDDO1 VDDO2 VDDO3
2C9> 2B9>
LTXD<8>\I LTXC<8>\I LRXD<8>\I LRXC<8>\I D_COMETB<7..0>\I
56 56 R184 R186
E4 E1 E3 D3 F6 E9 F7 D8 H3 J4 H4 F4 G5 F5 H6 J7 J6 H5 H7 J8 G6 J9 H8 G7 H9 J2 G3 G9 J3 H2 J1
BTFP BTPCM BTSIG BTCLK BRFP BRPCM BRSIG BRCLK D<0> D<1> D<2> D<3> D<4> D<5> D<6> D<7> A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> WRB RDB ALE INTB RSTB CSB VSSI1 VSSI2 VSSO1 VSSO2 VSSO3 TAVS1 TAVS2 TAVS3 TAVS4 RAVS1 RAVS2 QAVS
E
2C4< 2B4< 29E10<> 28E10<> 27E10<> 8D3<> 33E10<> 32E10<> 31E10<> 30E10<>
TXTIP1 TXTIP2 TXRING1 TXRING2 TDAT TFP RXTIP RXRING RDAT RCLKI PM4351 COMET TCLKO RSYNC TCLKI XCLK ATB TVREF RVREF TRIMF NC
D5 A2 C5 C4 C2 D1 C7 A8 E8 D9 C1 C9 B1 C3 B6 A4 D7 C8 B9
TXTIP<8>\I TXRING<8>\I
14G10< 14G10<
RXTIP<8>\I RXRING<8>\I
14F10> 14E10>
E
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8
RSYNC<8>\I TCLKI_B\I XCLK_B\I TVREF<8>\I
0.01UF R185 100K C134
8F10< 8D3> 8E3> 14G10>
8F3>
A_COMETB<8..0>\I VCC
D
8E3> 8E3> 6G10< 6B10> 8D3>
WRB\I RDB\I COMET_IRQB<8>\I RESETB\I COMET_CSB<8>\I
TMS TDI TDO TRSTB TCK
E2 G2 H1 F3 F1
TMS\I TDO7 TDO8 TRSTB\I TCK\I
6E10> 25D2> 27D1< 6D10> 6E10>
4.7K
R183
D
G1 F9
D4 E7 J5
B2 A3 B3 C6
B8 B7
C
D6
C
3.3 V
0.01UF
3.3 V
0.1UF
B
C128
C129
B
PLACE CAP ON THE VDDI PIN OF THE COMET
PLACE CAP ON THE VDDO PIN OF THE COMET
PMC-Sierra, Inc.
A DRAWING TITLE=COMET_BLOCK ABBREV=COMET_BLOCK LAST_MODIFIED=Thu Sep 16 13:46:32 1999 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD COMET BLOCK 9 ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE: 1.0 DATE: 99/07/27 PAGE:26 TRUE 1 OF 33 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET RAVD PINS
26G5> 26G5>
G
COMET_9_10_RAVD COMET_9_10_TAVD
0.01UF C130 1.0 R181
3.3 V
NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET TAVD PINS 3.3 V
F
3.3 V
F2 F8 D2 E6 G4 A1 B4 B5 A5 A9 A7 A6 G8
VCC
F
U54
TAVD1 TAVD2 TAVD3 TAVD4 RAVD1 RAVD2 QAVD BIAS
VDDI1 VDDI2 VDDO1 VDDO2 VDDO3
2C9> 2B9>
LTXD<9>\I LTXC<9>\I LRXD<9>\I LRXC<9>\I D_COMETB<7..0>\I
56 56 R240 R179
E4 E1 E3 D3 F6 E9 F7 D8 H3 J4 H4 F4 G5 F5 H6 J7 J6 H5 H7 J8 G6 J9 H8 G7 H9 J2 G3 G9 J3 H2 J1
BTFP BTPCM BTSIG BTCLK BRFP BRPCM BRSIG BRCLK D<0> D<1> D<2> D<3> D<4> D<5> D<6> D<7> A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> WRB RDB ALE INTB RSTB CSB VSSI1 VSSI2 VSSO1 VSSO2 VSSO3 TAVS1 TAVS2 TAVS3 TAVS4 RAVS1 RAVS2 QAVS
E
2C4< 2B4< 30E10<> 29E10<> 28E10<> 26E10<> 8D3<> 33E10<> 32E10<> 31E10<>
TXTIP1 TXTIP2 TXRING1 TXRING2 TDAT TFP RXTIP RXRING RDAT RCLKI PM4351 COMET TCLKO RSYNC TCLKI XCLK ATB TVREF RVREF TRIMF NC
D5 A2 C5 C4 C2 D1 C7 A8 E8 D9 C1 C9 B1 C3 B6 A4 D7 C8 B9
TXTIP<9>\I TXRING<9>\I
14D10< 14C10<
RXTIP<9>\I RXRING<9>\I
14C10> 14C10>
E
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8
RSYNC<9>\I TCLKI_B\I XCLK_B\I TVREF<9>\I
0.01UF R239 100K C127
8F10< 8D3> 8E3> 14D10>
8F3>
A_COMETB<8..0>\I VCC
4.7K R241
D
8E3> 8E3> 6G10< 6B10> 8D3>
WRB\I RDB\I COMET_IRQB<9>\I RESETB\I COMET_CSB<9>\I
TMS TDI TDO TRSTB TCK
E2 G2 H1 F3 F1
TMS\I TDO8 TDO9 TRSTB\I TCK\I
6E10> 26D2> 28D2< 6D10> 6E10>
D
G1 F9
D4 E7 J5
B2 A3 B3 C6
B8 B7
C
D6
C
3.3 V
0.01UF
3.3 V
0.1UF
B
C185
C133
B
PLACE CAP ON THE VDDI PIN OF THE COMET
PLACE CAP ON THE VDDO PIN OF THE COMET
PMC-Sierra, Inc.
A DRAWING TITLE=COMET_BLOCK ABBREV=COMET_BLOCK LAST_MODIFIED=Thu Sep 16 13:46:33 1999 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD COMET BLOCK 10 ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE: 1.0 DATE: 99/07/27 PAGE:27 TRUE 1 OF 33 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET RAVD PINS 3.3 V
2.2 R174 1UF C124
H
COMET_11_12_RAVD
29G7<
3.3 V
.47 R18
COMET_11_12_TAVD +
29G7<
G
NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET TAVD PINS 3.3 V
C27 22UF
0.01UF C123
3.3 V
1.0 R172
G
+ C26 68UF 3.3 V
F2 F8 D2 E6 G4 A1 B4 B5 A5 A9 A7 A6 G8
VCC
U55 F
F
TAVD1 TAVD2 TAVD3 TAVD4 RAVD1 RAVD2 QAVD BIAS
VDDI1 VDDI2 VDDO1 VDDO2 VDDO3
2C9> 2B9> 2C4< 2B4< 31E10<> 26E10<> 29E10<> 33E10<> 30E10<> 8D3<> 27E10<> 32E10<>
LTXD<10>\I LTXC<10>\I LRXD<10>\I LRXC<10>\I D_COMETB<7..0>\I
56 56 R176 R178
E4 E1 E3 D3 F6 E9 F7 D8 H3 J4 H4 F4 G5 F5 H6 J7 J6 H5 H7 J8 G6 J9 H8 G7 H9 J2 G3 G9 J3 H2 J1
BTFP BTPCM BTSIG BTCLK BRFP BRPCM BRSIG BRCLK D<0> D<1> D<2> D<3> D<4> D<5> D<6> D<7> A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> WRB RDB ALE INTB RSTB CSB VSSI1 VSSI2 VSSO1 VSSO2 VSSO3 TAVS1 TAVS2 TAVS3 TAVS4 RAVS1 RAVS2 QAVS
TXTIP1 TXTIP2 TXRING1 TXRING2 TDAT TFP RXTIP RXRING RDAT RCLKI PM4351 COMET TCLKO RSYNC TCLKI XCLK ATB TVREF RVREF TRIMF NC
D5 A2 C5 C4 C2 D1 C7 A8 E8 D9 C1 C9 B1 C3 B6 A4 D7 C8 B9
TXTIP<10>\I TXRING<10>\I
15G10< 15G10<
RXTIP<10>\I RXRING<10>\I
15F10> 15E10>
E
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8
RSYNC<10>\I TCLKI_B\I XCLK_B\I TVREF<10>\I
0.01UF R177 100K C126
8F10< 8D3> 8E3> 15G10>
E
8F3>
A_COMETB<8..0>\I VCC
4.7K R175
8E3> 8E3>
WRB\I RDB\I COMET_IRQB<10>\I RESETB\I COMET_CSB<10>\I
TMS TDI TDO TRSTB TCK
E2 G2 H1 F3 F1
TMS\I TDO9 TDO10 TRSTB\I TCK\I
6E10> 27D1> 29D1< 6D10> 6E10>
D
6G10< 6B10> 8D3>
D
G1 F9
D4 E7 J5
B2 A3 B3 C6
B8 B7
C
D6
C
3.3 V
0.01UF
3.3 V
0.1UF
C120
B
PLACE CAP ON THE VDDI PIN OF THE COMET
PLACE CAP ON THE VDDO PIN OF THE COMET
C121
B
PMC-Sierra, Inc.
A DRAWING TITLE=COMET_BLOCK ABBREV=COMET_BLOCK LAST_MODIFIED=Thu Sep 16 13:46:35 1999 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD COMET BLOCK 11 ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE: 1.0 DATE: 99/07/27 PAGE:28 TRUE 1 OF 33 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET RAVD PINS
28H5> 28G5>
G 3.3 V COMET_11_12_RAVD
1.0 0.01UF
COMET_11_12_TAVD
R173 C122
NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET TAVD PINS 3.3 V
3.3 V
F2 F8 D2 E6 G4 A1 B4 B5 A5 A9 A7 A6 G8
VCC
F
F U56
TAVD1 TAVD2 TAVD3 TAVD4 RAVD1 RAVD2 QAVD BIAS
VDDI1 VDDI2 VDDO1 VDDO2 VDDO3
2C9> 2B9> 2C4< 2B4<
LTXD<11>\I LTXC<11>\I LRXD<11>\I LRXC<11>\I D_COMETB<7..0>\I
56 56 R237 R171
E4 E1 E3 D3 F6 E9 F7 D8 H3 J4 H4 F4 G5 F5 H6 J7 J6 H5 H7 J8 G6 J9 H8 G7 H9 J2 G3 G9 J3 H2 J1
BTFP BTPCM BTSIG BTCLK BRFP BRPCM BRSIG BRCLK D<0> D<1> D<2> D<3> D<4> D<5> D<6> D<7> A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> WRB RDB ALE INTB RSTB CSB VSSI1 VSSI2 VSSO1 VSSO2 VSSO3 TAVS1 TAVS2 TAVS3 TAVS4 RAVS1 RAVS2 QAVS
TXTIP1 TXTIP2 TXRING1 TXRING2 TDAT TFP RXTIP RXRING RDAT RCLKI PM4351 COMET TCLKO RSYNC TCLKI XCLK ATB TVREF RVREF TRIMF NC TMS TDI TDO TRSTB TCK
D5 A2 C5 C4 C2 D1 C7 A8 E8 D9 C1 C9 B1 C3 B6 A4 D7 C8 B9
TXTIP<11>\I TXRING<11>\I
15D10< 15C10<
RXTIP<11>\I RXRING<11>\I
15C10> 15C10>
E
28E10<> 27E10<> 26E10<> 8D3<> 33E10<> 32E10<> 31E10<> 30E10<>
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8
E RSYNC<11>\I TCLKI_B\I XCLK_B\I TVREF<11>\I
0.01UF R236 100K C119
8F10< 8D3> 8E3> 15D10>
8F3>
A_COMETB<8..0>\I VCC
4.7K R238
E2 G2 H1 F3 F1
TMS\I TDO10 TDO11 TRSTB\I TCK\I
D
8E3> 8E3> 6G10< 6B10> 8D3>
WRB\I RDB\I COMET_IRQB<11>\I RESETB\I COMET_CSB<11>\I
6E10> 28D2> 30D1< 6D10> 6E10>
D
G1 F9
D4 E7 J5
B2 A3 B3 C6
B8 B7
C
D6
C
3.3 V
0.01UF
3.3 V
0.1UF
B
C184
C125
PLACE CAP ON THE VDDI PIN OF THE COMET
PLACE CAP ON THE VDDO PIN OF THE COMET
B
PMC-Sierra, Inc.
A DRAWING TITLE=COMET_BLOCK ABBREV=COMET_BLOCK LAST_MODIFIED=Thu Sep 16 13:46:36 1999 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD COMET BLOCK 12 ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE: 1.0 DATE: 99/07/27 PAGE:29 TRUE 1 OF 33 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET RAVD PINS 3.3 V
2.2 R166 1UF C116
COMET_13_14_RAVD
31G7<
G 3.3 V
.47 R19
G
COMET_13_14_TAVD +
1.0 0.01UF R164 C115
31G7<
NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET TAVD PINS 3.3 V
C31 22UF
3.3 V
+ C30 68UF F 3.3 V
F2 F8 D2 E6 G4 A1 B4 B5 A5 A9 A7 A6 G8
VCC
F
U57
TAVD1 TAVD2 TAVD3 TAVD4 RAVD1 RAVD2 QAVD BIAS
VDDI1 VDDI2 VDDO1 VDDO2 VDDO3
2C9> 2B9>
LTXD<12>\I LTXC<12>\I LRXD<12>\I LRXC<12>\I D_COMETB<7..0>\I
56 56 R168 R170
E4 E1 E3 D3 F6 E9 F7 D8 H3 J4 H4 F4 G5 F5 H6 J7 J6 H5 H7 J8 G6 J9 H8 G7 H9 J2 G3 G9 J3 H2 J1
BTFP BTPCM BTSIG BTCLK BRFP BRPCM BRSIG BRCLK D<0> D<1> D<2> D<3> D<4> D<5> D<6> D<7> A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> WRB RDB ALE INTB RSTB CSB VSSI1 VSSI2 VSSO1 VSSO2 VSSO3 TAVS1 TAVS2 TAVS3 TAVS4 RAVS1 RAVS2 QAVS
E
2C4< 2B4< 28E10<> 27E10<> 26E10<> 8D3<> 33E10<> 32E10<> 31E10<> 29E10<>
TXTIP1 TXTIP2 TXRING1 TXRING2 TDAT TFP RXTIP RXRING RDAT RCLKI PM4351 COMET TCLKO RSYNC TCLKI XCLK ATB TVREF RVREF TRIMF NC
D5 A2 C5 C4 C2 D1 C7 A8 E8 D9 C1 C9 B1 C3 B6 A4 D7 C8 B9
TXTIP<12>\I TXRING<12>\I
16G10< 16G10<
RXTIP<12>\I RXRING<12>\I
16F10> 16E10>
E
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8
RSYNC<12>\I TCLKI_B\I XCLK_B\I TVREF<12>\I
0.01UF R169 100K C118
8F10< 8D3> 8E3> 16G10>
8F3>
A_COMETB<8..0>\I VCC
D
8E3> 8E3> 6G10< 6B10> 8D3>
WRB\I RDB\I COMET_IRQB<12>\I RESETB\I COMET_CSB<12>\I
TMS TDI TDO TRSTB TCK
E2 G2 H1 F3 F1
TMS\I TDO11 TDO12 TRSTB\I TCK\I
6E10> 29D1> 31D1< 6D10> 6E10>
4.7K
R167
D
G1 F9
D4 E7 J5
B2 A3 B3 C6
B8 B7
C
D6
C
3.3 V
0.01UF
3.3 V
0.1UF
B
C112
C113
B
PLACE CAP ON THE VDDI PIN OF THE COMET
PLACE CAP ON THE VDDO PIN OF THE COMET
PMC-Sierra, Inc.
A DRAWING TITLE=COMET_BLOCK ABBREV=COMET_BLOCK LAST_MODIFIED=Thu Sep 16 13:46:37 1999 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD COMET BLOCK 13 ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE: 1.0 DATE: 99/07/27 PAGE:30 TRUE 1 OF 33 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET RAVD PINS
30G5> 30G5>
G
COMET_13_14_RAVD COMET_13_14_TAVD
0.01UF C114 1.0 R165
3.3 V
NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET TAVD PINS 3.3 V
3.3 V F
F2 F8 D2 E6 G4 A1 B4 B5 A5 A9 A7 A6 G8
VCC F U58
TAVD1 TAVD2 TAVD3 TAVD4 RAVD1 RAVD2 QAVD BIAS
VDDI1 VDDI2 VDDO1 VDDO2 VDDO3
2C9> 2B9> 2C4<
LTXD<13>\I LTXC<13>\I LRXD<13>\I LRXC<13>\I D_COMETB<7..0>\I
56 56 R234 R163
E4 E1 E3 D3 F6 E9 F7 D8 H3 J4 H4 F4 G5 F5 H6 J7 J6 H5 H7 J8 G6 J9 H8 G7 H9 J2 G3 G9 J3 H2 J1
BTFP BTPCM BTSIG BTCLK BRFP BRPCM BRSIG BRCLK D<0> D<1> D<2> D<3> D<4> D<5> D<6> D<7> A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> WRB RDB ALE INTB RSTB CSB VSSI1 VSSI2 VSSO1 VSSO2 VSSO3 TAVS1 TAVS2 TAVS3 TAVS4 RAVS1 RAVS2 QAVS
TXTIP1 TXTIP2 TXRING1 TXRING2 TDAT TFP RXTIP RXRING RDAT RCLKI PM4351 COMET TCLKO RSYNC TCLKI XCLK ATB TVREF RVREF TRIMF NC
D5 A2 C5 C4 C2 D1 C7 A8 E8 D9 C1 C9 B1 C3 B6 A4 D7 C8 B9
TXTIP<13>\I TXRING<13>\I
16D10< 16C10<
E
2B4< 28E10<> 27E10<> 26E10<> 8D3<> 33E10<> 32E10<> 30E10<> 29E10<>
RXTIP<13>\I RXRING<13>\I
16C10> 16C10>
E
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8
RSYNC<13>\I TCLKI_B\I XCLK_B\I TVREF<13>\I
0.01UF R233 100K C111
8F10< 8D3> 8E3> 16D10>
8F3>
A_COMETB<8..0>\I VCC
4.7K R235
D
8E3> 8E3> 6G10< 6B10> 8D3>
WRB\I RDB\I COMET_IRQB<13>\I RESETB\I COMET_CSB<13>\I
TMS TDI TDO TRSTB TCK
E2 G2 H1 F3 F1
TMS\I TDO12 TDO13 TRSTB\I TCK\I
6E10> 30D1> 32D1< 6D10> 6E10>
D
G1 F9
D4 E7 J5
B2 A3 B3 C6
B8 B7
C
D6
C
3.3 V
0.01UF
3.3 V
0.1UF
B PLACE CAP ON THE VDDI PIN OF THE COMET PLACE CAP ON THE VDDO PIN OF THE COMET
C183
C117
B
PMC-Sierra, Inc.
A DRAWING TITLE=COMET_BLOCK ABBREV=COMET_BLOCK LAST_MODIFIED=Thu Sep 16 13:46:38 1999 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD COMET BLOCK 14 ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE: 1.0 DATE: 99/07/27 PAGE:31 TRUE 1 OF 33 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET RAVD PINS 3.3 V
2.2 R158 1UF C108
COMET_15_16_RAVD
33G7<
G 3.3 V
.47 R20
G COMET_15_16_TAVD +
1.0 0.01UF R157 C107
33G7<
NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET TAVD PINS 3.3 V
C35 22UF
3.3 V
C34 68UF F
+
3.3 V
F2 F8 D2 E6 G4 A1 B4 B5 A5 A9 A7 A6 G8
VCC
F U59
TAVD1 TAVD2 TAVD3 TAVD4 RAVD1 RAVD2 QAVD BIAS
VDDI1 VDDI2 VDDO1 VDDO2 VDDO3
2C9> 2B9> 2C4<
LTXD<14>\I LTXC<14>\I LRXD<14>\I LRXC<14>\I D_COMETB<7..0>\I
56 56 R160 R162
E4 E1 E3 D3 F6 E9 F7 D8 H3 J4 H4 F4 G5 F5 H6 J7 J6 H5 H7 J8 G6 J9 H8 G7 H9 J2 G3 G9 J3 H2 J1
BTFP BTPCM BTSIG BTCLK BRFP BRPCM BRSIG BRCLK D<0> D<1> D<2> D<3> D<4> D<5> D<6> D<7> A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> WRB RDB ALE INTB RSTB CSB VSSI1 VSSI2 VSSO1 VSSO2 VSSO3 TAVS1 TAVS2 TAVS3 TAVS4 RAVS1 RAVS2 QAVS
TXTIP1 TXTIP2 TXRING1 TXRING2 TDAT TFP RXTIP RXRING RDAT RCLKI PM4351 COMET TCLKO RSYNC TCLKI XCLK ATB TVREF RVREF TRIMF NC
D5 A2 C5 C4 C2 D1 C7 A8 E8 D9 C1 C9 B1 C3 B6 A4 D7 C8 B9
TXTIP<14>\I TXRING<14>\I
17G10< 17G10<
E
2B4< 28E10<> 27E10<> 26E10<> 8D3<> 33E10<> 31E10<> 30E10<> 29E10<>
RXTIP<14>\I RXRING<14>\I
17F10> 17E10>
E
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8
RSYNC<14>\I TCLKI_B\I XCLK_B\I TVREF<14>\I
0.01UF R161 100K C110
8F10< 8D3> 8E3> 17G10>
8F3>
A_COMETB<8..0>\I VCC
4.7K R159
D
8E3> 8E3> 6G10< 6B10> 8D3>
WRB\I RDB\I COMET_IRQB<14>\I RESETB\I COMET_CSB<14>\I
TMS TDI TDO TRSTB TCK
E2 G2 H1 F3 F1
TMS\I TDO13 TDO14 TRSTB\I TCK\I
6E10> 31D1> 33D2< 6D10> 6E10>
D
G1 F9
D4 E7 J5
B2 A3 B3 C6
B8 B7
C
D6
C
3.3 V
0.01UF
3.3 V
0.1UF
B
C104
C105
B
PLACE CAP ON THE VDDI PIN OF THE COMET
PLACE CAP ON THE VDDO PIN OF THE COMET
PMC-Sierra, Inc.
A DRAWING TITLE=COMET_BLOCK ABBREV=COMET_BLOCK LAST_MODIFIED=Thu Sep 16 13:46:40 1999 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD COMET BLOCK 15 ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE: 1.0 DATE: 99/07/27 PAGE:32 TRUE 1 OF 33 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
G
NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET RAVD PINS
32G5> 32G5>
3.3 V COMET_15_16_RAVD
1.0
COMET_15_16_TAVD
0.01UF C106
R156
NOTE: PLACE ONE FILTER NETWORK FOR TWO COMET TAVD PINS
3.3 V
F
3.3 V
F2 F8 D2 E6 G4 A1 B4 B5 A5 A9 A7 A6 G8
VCC
F
U60
TAVD1 TAVD2 TAVD3 TAVD4 RAVD1 RAVD2 QAVD BIAS
VDDI1 VDDI2 VDDO1 VDDO2 VDDO3
2C9> 2B9> 2C4<
LTXD<15>\I LTXC<15>\I LRXD<15>\I LRXC<15>\I D_COMETB<7..0>\I
56 56 R231 R155
E4 E1 E3 D3 F6 E9 F7 D8 H3 J4 H4 F4 G5 F5 H6 J7 J6 H5 H7 J8 G6 J9 H8 G7 H9 J2 G3 G9 J3 H2 J1
BTFP BTPCM BTSIG BTCLK BRFP BRPCM BRSIG BRCLK D<0> D<1> D<2> D<3> D<4> D<5> D<6> D<7> A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> WRB RDB ALE INTB RSTB CSB VSSI1 VSSI2 VSSO1 VSSO2 VSSO3 TAVS1 TAVS2 TAVS3 TAVS4 RAVS1 RAVS2 QAVS
TXTIP1 TXTIP2 TXRING1 TXRING2 TDAT TFP RXTIP RXRING RDAT RCLKI PM4351 COMET TCLKO RSYNC TCLKI XCLK ATB TVREF RVREF TRIMF NC
D5 A2 C5 C4 C2 D1 C7 A8 E8 D9 C1 C9 B1 C3 B6 A4 D7 C8 B9
TXTIP<15>\I TXRING<15>\I
17D10< 17C10<
E
2B4< 32E10<> 31E10<> 27E10<> 26E10<> 8D3<> 30E10<> 29E10<> 28E10<>
RXTIP<15>\I RXRING<15>\I
17C10> 17C10>
E
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8
RSYNC<15>\I TCLKI_B\I XCLK_B\I TVREF<15>\I
0.01UF 100K R230 C103
8F10< 8D3> 8E3> 17D10>
8F3>
A_COMETB<8..0>\I VCC
4.7K R232
D
8E3> 8E3> 6G10< 6B10> 8D3>
WRB\I RDB\I COMET_IRQB<15>\I RESETB\I COMET_CSB<15>\I
TMS TDI TDO TRSTB TCK
E2 G2 H1 F3 F1
TMS\I TDO14 TDO_COMET15\I TRSTB\I TCK\I
6E10> 32D1> 2D4< 6D10> 6E10>
D
G1 F9
D4 E7 J5
B2 A3 B3 C6
B8 B7
C
D6
C
3.3 V
0.01UF
3.3 V
0.1UF
B
C182
C109
B
PLACE CAP ON THE VDDI PIN OF THE COMET
PLACE CAP ON THE VDDO PIN OF THE COMET
PMC-Sierra, Inc.
A DRAWING TITLE=COMET_BLOCK ABBREV=COMET_BLOCK LAST_MODIFIED=Thu Sep 16 13:46:41 1999 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD COMET BLOCK 16 ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE: 1.0 DATE: 99/07/27 PAGE:33 TRUE 1 OF 33 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
J24 RX_0
T TN RN R S
T TN RN R S 100 R224
A1 C1 A2 C2 A3 C3
GND=GND1 71624-2004 P3 A1 B1 B1 C1 D1 D1 A2 C2 A3 C3 A4 C4 A5 C5 A6 C6 A7 C7 A8 C8 A9 C9 B2 D2 B3 D3 B4 D4 B5 D5 B6 D6 B7 D7 B8 D8 B9 D9 B10 D10 B11 D11 B12 D12 B13 D13 B14 D14 B15 D15 B16 D16 B17 D17 B18 D18 B19 D19 B20 D20 B21 D21 B22 D22 B23 D23 B24 D24 B25 D25 B26 D26 B27 D27 B28 D28 B29 D29 B30 D30 B31 D31 B32 D32 B33 D33 B34 D34 B35 D35 B36 D36 B37 D37 B38 D38 B39 D39 B40 D40
B2 D2 B3 D3 B4 D4 B5 D5 B6 D6 B7 D7 B8 D8 B9 D9 B10 D10 B11 D11 B12 D12 B13 D13 B14 D14 B15 D15 B16 D16 B17 D17 B18 D18 B19 D19 B20 D20 B21 D21 B22 D22 B23 D23 B24 D24 B25 D25 B26 D26 B27 D27 B28 D28 B29 D29 B30 D30 B31 D31 B32 D32 B33 D33 B34 D34 B35 D35 B36 D36 B37 D37 B38 D38 B39 D39 B40 D40
OUT_TIP_0 OUT_RING_0
34G7< 34G7<
OUT_TIP_1 OUT_RING_1
34G7< 34G7<
BANTAM G
34H5> 34H5>
OUT_TIP_0 OUT_RING_0
A4 C4 A5 C5 A6 C6
G OUT_TIP_2 OUT_RING_2
34F7< 34F7<
34G5> 34G5>
OUT_TIP_1 OUT_RING_1
A7 C7 A8 C8
TX_3 J22
100 R154 T TN RN R S
34G5> 34G5>
OUT_TIP_2 OUT_RING_2
A9 C9 A10 C10
T TN RN R S
A10 C10 A11 C11 A12 C12 A13 C13 A14 C14 A15 C15 A16 C16 A17 C17 A18 C18 A19 C19 A20 C20 A21 C21 A22 C22 A23 C23 A24 C24 A25 C25 A26 C26 A27 C27 A28 C28 A29 C29 A30 C30 A31 C31 A32 C32 A33 C33 A34 C34 A35 C35 A36 C36 A37 C37 A38 C38 A39 C39 A40 C40
BANTAM OUT_TIP_4 OUT_RING_4
34F7< 34F7<
F
RX_4
J21
T TN RN R S
T TN RN R S 100 R153
A11 C11 A12 C12 A13 C13
F
OUT_TIP_5 OUT_RING_5
34E7< 34E7<
BANTAM
34F5> 34F5>
OUT_TIP_4 OUT_RING_4
A14 C14 A15 C15 A16 C16
OUT_TIP_6 OUT_RING_6
34E7< 34E7<
34F5> 34F5>
OUT_TIP_5 OUT_RING_5
A17 C17 A18 C18
J20 TX_7
100 R152 T TN RN R S
E
34E5> 34E5>
OUT_TIP_6 OUT_RING_6
A19 C19 A20 C20
T TN RN R S
E
BANTAM OUT_TIP_8 OUT_RING_8
34D7< 34D7<
RX_8
J17
T TN RN R S
T TN RN R S 100 R99
A21 C21 A22 C22 A23 C23
OUT_TIP_9 OUT_RING_9
34D7< 34D7<
BANTAM D
34E5> 34E5>
OUT_TIP_8 OUT_RING_8
A24 C24 A25 C25 A26 C26
D OUT_TIP_10 OUT_RING_10
34C7< 34C7<
34D5> 34D5>
OUT_TIP_9 OUT_RING_9
A27 C27 A28 C28
J8 TX_11
100 R86 T TN RN R S
34D5> 34D5>
OUT_TIP_10 OUT_RING_10
A29 C29 A30 C30
T TN RN R S
BANTAM OUT_TIP_12 OUT_RING_12
34C7< 34C7<
C
RX_12
J7
T TN RN R S
T TN RN R S 100 R85
A31 C31 A32 C32 A33 C33
C
OUT_TIP_13 OUT_RING_13
34B7< 34B7<
BANTAM
34C5> 34C5>
OUT_TIP_12 OUT_RING_12
A34 C34 A35 C35 A36 C36
OUT_TIP_14 OUT_RING_14
34B7< 34B7<
34C5> 34C5>
OUT_TIP_13 OUT_RING_13
A37 C37 A38 C38
TX_15 J6
100 R84 T TN RN R S
B
34B5> 34B5>
OUT_TIP_14 OUT_RING_14
A39 C39 A40 C40
T TN RN R S
B
BANTAM
GND1
GND1
PMC-Sierra, Inc.
A DRAWING TITLE=LOOPBACK_CARD ABBREV=LOOPBACK_CARD LAST_MODIFIED=Thu Sep 16 13:46:12 1999 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-990354 TITLE: DSLAM LINE CARD LOOPBACK TEST JIG CARD ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE: 1.0 DATE: 99/08/20 PAGE:34 TRUE 1 OF 33 A
RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
APPENDIX B: LAYOUT This layout contains 13 pages as follows: Sheet 1: Mechanical description Sheet 2: Component Top Sheet 3: Silkscreen Top Sheet 4: Top Layer Sheet 5: GND Plane Sheet 6: VCC Plane Sheet 7: Sig1 Layer Sheet 8: Sig2 Layer Sheet 9: 3V3 Plane Sheet 10: GND Plane Sheet 11: Bottom Layer Sheet 12: Component Bottom Sheet 13: Silkscreen Bottom The PCB was designed to have the Loopback Test Jig card as a breakout of the board.
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
APPENDIX C: VHDL CODE FOR FPGA -- -------------------------------------------------------------------- -------------------------------------------------------------------- PMC-Sierra, Inc. -- PROPRIETARY AND CONFIDENTIAL --- Copyright 1999 PMC-Sierra, Inc. --- All rights reserved. No part of this documentation or computer -- program may be used, modified, reproduced, or distributed in any -- form by any means without the prior written permission of -- PMC-Sierra, Inc. --- This documentation and computer program contains trade secrets, -- confidential business information and commercial or financial -- information (collectively, the "Information") of PMC-Sierra, Inc., -- or unlawful disclosure of any or all of the Information may cause -- irreparable harm and result in significant commercial and -- competitive loss to PMC-Sierra, Inc. -- -------------------------------------------------------------------- -------------------------------------------------------------------- PMC-Sierra, Inc. -- 105 - 8555 Baxter Place -- Burnaby, B.C. -- Canada V5A 4V7 -- Tel: 604-415-6000 -- Fax: 604-415-6206 -- email: apps@pmc-sierra.com -- -------------------------------------------------------------------- Project : PMC-990354 -- File Name : dslam_line_top.vhd -- Path : -- Designer : SW --- Revision History -- Issue Date Initials Description -- 1 08/17/99 SW Initial Release -- 1.1 09/17/99 WT debugging errors, -added comments -- 1.2 11/03/99 WT Added buffer components -changed internal fpga by -adding initialization on reset --- Function
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
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DSLAM REFERENCE DESIGN: LINE CARD
-- This is the top level of the VHDL code required for the DSLAM LINE -- reference design. The code creates some registers, does some muxing -- for various timing options, supplies some glue logic for microprocessor -- signals and acts as a buffer for the address and data bus. ----------------------------------------------------------------------
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library a42mx; entity dslam_line_top is port ( a_m : in std_logic_vector (23 downto 0); rwb_m : in std_logic; asb : in std_logic; dsb : in std_logic; siz0 : in std_logic; siz1 : in std_logic; cs0b : in std_logic; cs1b : in std_logic; cs2b : in std_logic; cs3b : in std_logic; d_m : inout std_logic_vector (7 downto 0); rsync : in std_logic_vector (15 downto 0); rx8k : in std_logic; mode : in std_logic; uweb : out std_logic; lweb : out std_logic; oeb : out std_logic; deb_mem : out std_logic; a_cometa : out std_logic_vector (8 downto 0); a_cometb : out std_logic_vector (8 downto 0); a : out std_logic_vector (7 downto 0); d_cometa : inout std_logic_vector (7 downto 0); d_cometb : inout std_logic_vector (7 downto 0); rdb : out std_logic; wrb : out std_logic; duplex_csb : out std_logic; tx8k : out std_logic; xclk_a : out std_logic;
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DSLAM REFERENCE DESIGN: LINE CARD
xclk_b : out std_logic; comet_led : out std_logic_vector (3 downto 0); tclki_a : out std_logic; tclki_b : out std_logic; d : inout std_logic_vector (7 downto 0); comet_csb : out std_logic_vector (15 downto 0); xclk_input : in std_logic; expansion_port1 : inout std_logic_vector (6 downto 0); expansion_port2 : inout std_logic_vector (6 downto 0); fpga1 : in std_logic; fpga2 : in std_logic; fpga3 : in std_logic; fpga4 : in std_logic ); end dslam_line_top; architecture dslam_line_top_arch of dslam_line_top is --- added by WT -- buffer components added for A42MX36 specific layout problems -component BUFF port (A : in std_logic; Y : out std_logic ); end component; type regtype is array (0 to 3) of std_logic_vector (7 downto 0); signal fpga_reg : regtype; --- added by WT -- signals used by buffers to eliminate long horizontal tracks created in -- device during layout -signal a_m_buff : std_logic_vector (8 downto 0); signal d_m_buff : std_logic_vector (7 downto 0); begin --- This section is for the internal fpga registers used to control
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DSLAM REFERENCE DESIGN: LINE CARD
-- the timing multiplexing functions -process (dsb, fpga4) -- This process provides write ability to the internal fpga registers -- The fpga is placed on chip select 2 of the microprocessor -- The base address of the fpga registers are 0x1001 1000 (hex) -- On reset to the board, the fpga registers are initialized to their -- default value. -- note fpga4 is tied to signal RESETB -- fpga_reg(0) = tclk_a select = 2.048MHz = "00010000" -- fpga_reg(1) = tclk_b select = 2.048MHz = "00010000" -- fpga_reg(2) = tx8k select = COMET#0 RSYNC = "00000000" -- fpga_reg(3) = comet_leds = OFF = "00000000" variable int: integer range 0 to 3 ; begin if fpga4 = '0' then fpga_reg(0) <= "00010000"; fpga_reg(1) <= "00010000"; fpga_reg(2) <= "00000000"; fpga_reg(3) <= "00000000"; end if; if fpga4 = '1' then if (cs2b = '0') and (a_m(16 downto 12) = "11000") and (rwb_m = '0') and (dsb = '0') then int := to_integer(unsigned(a_m(1 downto 0))); fpga_reg(int) <= d_m; end if; end if; end process; --- COMET #0 - #7 tclk select -tclki_a <= rsync(to_integer(unsigned(fpga_reg(0)))) when (fpga_reg(0)(7 downto 4) = "0000") else rx8k when (fpga_reg(0)(4 downto 0) = "11111") else xclk_input; --- COMET #8 - #15 tclk select -tclki_b <= rsync(to_integer(unsigned(fpga_reg(1)))) when (fpga_reg(1)(7 downto 4) = "0000")
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
else rx8k when (fpga_reg(1)(4 downto 0) = "11111") else xclk_input; --- S/UNI-DUPLEX tx8k input select -tx8k <= rsync(to_integer(unsigned(fpga_reg(2)(3 downto 0)))); --- COMET Status LED control -comet_led <= fpga_reg(3)(3 downto 0); --- COMET XCLK Buffer -xclk_a <= xclk_input; xclk_b <= xclk_input; --- This section added to help debug internal fpga registers -- fpga3 is used as an debug enable '1' is enable '0' is highZ -process (fpga3, fpga_reg) begin if fpga3 = '0' then expansion_port1 <= "ZZZZZZZ"; expansion_port2 <= "ZZZZZZZ"; end if; if fpga3 = '1' then expansion_port1 <= fpga_reg(0)(6 downto 0); expansion_port2 <= fpga_reg(1)(6 downto 0); end if; end process; --- This section is for the microprocessor glue logic signals -lweb <= not (((not siz0) or(a_m(0))) and (not cs1b) and (not rwb_m)) when mode = '1' else not (((not siz0) or(a_m(0))) and (not (cs1b and cs0b)) and (not rwb_m)); uweb <= not ((not rwb_m) and (not a_m(0)) and (not cs1b)) when mode = '1' else not ((not rwb_m) and (not a_m(0)) and (not (cs1b and cs0b)));
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
oeb <= not (rwb_m and (not cs1b)) when mode = '1' else not (rwb_m and (not (cs1b and cs0b))); wrb <= rwb_m; rdb <= not rwb_m; deb_mem <= cs0b and cs1b; --- This section is the address buffers -a_m_b0: BUFF port map (A => a_m(0), Y => a_m_buff(0)); a_m_b1: BUFF port map (A => a_m(1), Y => a_m_buff(1)); a_m_b2: BUFF port map (A => a_m(2), Y => a_m_buff(2)); a_m_b3: BUFF port map (A => a_m(3), Y => a_m_buff(3)); a_m_b4: BUFF port map (A => a_m(4), Y => a_m_buff(4)); a_m_b5: BUFF port map (A => a_m(5), Y => a_m_buff(5)); a_m_b6: BUFF port map (A => a_m(6), Y => a_m_buff(6)); a_m_b7: BUFF port map (A => a_m(7), Y => a_m_buff(7)); a_m_b8: BUFF port map (A => a_m(8), Y => a_m_buff(8)); a <= a_m_buff(7 downto 0); a_cometa <= a_m_buff; a_cometb <= a_m_buff; --- This section is the data bus buffers -d_m_b0: BUFF port map (A => d_m(0), Y => d_m_buff(0)); d_m_b1: BUFF port map (A => d_m(1), Y => d_m_buff(1)); d_m_b2: BUFF port map (A => d_m(2), Y => d_m_buff(2)); d_m_b3: BUFF port map (A => d_m(3), Y => d_m_buff(3)); d_m_b4: BUFF port map (A => d_m(4), Y => d_m_buff(4)); d_m_b5: BUFF port map (A => d_m(5), Y => d_m_buff(5)); d_m_b6: BUFF port map (A => d_m(6), Y => d_m_buff(6)); d_m_b7: BUFF port map (A => d_m(7), Y => d_m_buff(7)); d_cometa <= d_m_buff when ((cs2b = '0') and (rwb_m = '0') and (a_m(16) = '0') and (a_m(15) = '0')) else "ZZZZZZZZ"; d_cometb <= d_m_buff when ((cs2b = '0') and (rwb_m = '0') and (a_m(16) = '0') and (a_m(15) = '1')) else "ZZZZZZZZ";
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
d <= d_m_buff when ((cs2b = '0') and (rwb_m = '0') and (a_m(16) = '1') and (a_m(15) = '0')) else "ZZZZZZZZ"; d_m <= d_cometa when ((cs2b = '0') and (rwb_m = '1') and (a_m(16) = '0') and (a_m(15) = '0')) else d_cometb when ((cs2b = '0') and (rwb_m = '1') and (a_m(16) = '0') and (a_m(15) = '1')) else d when ((cs2b = '0') and (rwb_m = '1') and (a_m(16) = '1') and (a_m(15) = '0')) else "ZZZZZZZZ"; --- This section is the chip select logic -comet_csb(0) <= not ((not cs2b) and (not a_m(16)) and (not a_m(15)) and (not a_m(14)) and (not a_m(13)) and (not a_m(12))); comet_csb(1) <= not ((not cs2b) and (not a_m(16)) and (not a_m(15)) and (not a_m(14)) and (not a_m(13)) and ( a_m(12))); comet_csb(2) <= not ((not cs2b) and (not a_m(16)) and (not a_m(15)) and (not a_m(14)) and ( a_m(13)) and (not a_m(12))); comet_csb(3) <= not ((not cs2b) and (not a_m(16)) and (not a_m(15)) and (not a_m(14)) and ( a_m(13)) and ( a_m(12))); comet_csb(4) <= not ((not cs2b) and (not a_m(16)) and (not a_m(15)) and ( and (not a_m(13)) and (not a_m(12))); comet_csb(5) <= not ((not cs2b) and (not a_m(16)) and (not a_m(15)) and ( and (not a_m(13)) and ( a_m(12))); comet_csb(6) <= not ((not cs2b) and (not a_m(16)) and (not a_m(15)) and ( and ( a_m(13)) and (not a_m(12))); comet_csb(7) <= not ((not cs2b) and (not a_m(16)) and (not a_m(15)) and ( and ( a_m(13)) and ( a_m(12))); comet_csb(8) <= not ((not cs2b) and (not a_m(16)) and ( and (not a_m(13)) and (not a_m(12))); comet_csb(9) <= not ((not cs2b) and (not a_m(16)) and ( and (not a_m(13)) and ( a_m(12))); a_m(14)) a_m(14)) a_m(14)) a_m(14))
a_m(15)) and (not a_m(14)) a_m(15)) and (not a_m(14))
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
comet_csb(10) <= not ((not cs2b) and (not a_m(16)) and ( a_m(14)) and ( a_m(13)) and (not a_m(12))); comet_csb(11) <= not ((not cs2b) and (not a_m(16)) and ( a_m(14)) and ( a_m(13)) and ( a_m(12))); comet_csb(12) <= not ((not cs2b) and (not a_m(16)) and ( and (not a_m(13)) and (not a_m(12))); comet_csb(13) <= not ((not cs2b) and (not a_m(16)) and ( and (not a_m(13)) and ( a_m(12))); comet_csb(14) <= not ((not cs2b) and (not a_m(16)) and ( and ( a_m(13)) and (not a_m(12))); comet_csb(15) <= not ((not cs2b) and (not a_m(16)) and ( and ( a_m(13)) and ( a_m(12)));
a_m(15)) and (not a_m(15)) and (not a_m(15)) and ( a_m(15)) and ( a_m(15)) and ( a_m(15)) and ( a_m(14)) a_m(14)) a_m(14)) a_m(14))
duplex_csb <= not ((not cs2b) and ( a_m(16)) and (not a_m(15)) and (not a_m(14)) and (not a_m(13)) and (not a_m(12))); end dslam_line_top_arch;
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
APPENDIX D: BILL OF MATERIALS This table shows the materials needed to assemble the Line Card. Table 8
Item 1 2 3 4 5
- Bill of Materials
Description 1N5817_-1N5817M 74F08_SOIC-BASE 74FCT16245_1_SSO P48- BASE 74FCT245_1_SOIC20 W-BASE A42MX36_PQ208_SO CKET 2-BASE AT27C4096_PLCC100NS BANTAM-BASE CAPACITOR-0.01UF, 50V, X7R_603 Vendor Part Number 1N5817M 74F08 74FCT16245T 74FCT245T A42MX36_PQ208 & YAMAICHI IC149208-0 AT27C4096-10JI ELECTRO SONIC -PC-834-J-(BLACK) DIGIKEY PCC103BVCT-ND Reference Designator D5 U65 U42 U43, U44, U62 U61 Qty 1 1 1 3 1
6 7 8
U37 J6-J8, J17, J20-J22, J24 C103, C105-C107, C109-C111, C113-C115, C117-C119, C121C123, C125-C127, C129-C131, C133-C135, C137-C139, C141C143, C145-C147, C149-C152, C154, C155, C157-C159, C161C163, C165, C166, C175, C176, C181, C203-C205, C207, C209, C211, C213, C215, C217, C218, C225, C229, C231 C1, C48, C49, C55, C56, C58, C59, C63, C73, C75, C76, C78C94, C96-C102, C104, C112, C120, C128, C136, C144, C153, C160, C167-C174, C177C180, C182-C202, C206, C208, C210, C212, C214, C216, C219-C224, C226-C228, C230, C232
1 8 64
9
CAPACITOR-0.1UF, 16V, X7R_603
PANASONIC -- ECJ1VB1C104K
93
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
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DSLAM REFERENCE DESIGN: LINE CARD
Item 10 11 12 13 14 15 16 17 18
Description CAPACITOR-0.22UF, 10V, X7R_603 CAPACITOR-0.33UF, 35V, TANT TEH CAPACITOR-1000UF, 10V, ELECTRO_SA CAPACITOR-10UF, 16V, TANT TEH CAPACITOR-10UF, 6.3V, TANT TE CAPACITOR-1UF, 16V, TANT TEH CAPACITOR-22UF, 16V, TANT TEH CAPACITOR-22UF, 6.3V, TANT TEH CAPACITOR-4.7UF, 10V, TANT TEH CAPACITOR-4.7UF, 16V, TANT TEH CAPACITOR-47UF, 10V, TANT TEH CAPACITOR-68UF, 6.3V, TANT TEH COMET_CABGABASE CONN160_716264000-B ASEGND=CHA CONN160_MALE_716 24-2 004-BASE-GA CPCI_ESD_STRIP_B OTTO M_EDGEBASE CY7C1049-25NS
Vendor Part Number DIGI-KEY -PCC1749CT-ND DIGI-KEY -PCT6334CT-ND DIGI-KEY -PCE3178CT-ND DIGI-KEY -PCT3106CT-ND DIGI-KEY -PCS1106CT-ND DIGI-KEY -PCT3105CT-ND DIGI-KEY -PCT3226CT-ND DIGI-KEY -PCT1226CT-ND DIGI-KEY -PCT2475CT-ND DIGI-KEY -PCT3475CT-ND DIGI-KEY -PCT2476CT-ND DIGI-KEY -PCT1686CT-ND PM4351-NI MOLEX -- 716264000 MOLEX -- 716242004 PART OF PCB
Reference Designator C65-C72 C61 C62 C43, C44, C64 C2, C74, C77, C95 C54, C108, C116, C124, C132, C140, C148, C156, C164 C3, C36-C42, C46, C47 C7, C11, C15, C19, C23, C27, C31, C35, C45, C50-C52 C4, C6, C8, C10, C12, C14, C16, C17, C20, C21, C24, C25, C28, C29, C32, C33 C57, C60 C53 C5, C9, C13, C18, C22, C26, C30, C34 U45-U60 P2
Qty 8 1 1 3 4 9 10 12 16
19 20 21 22 23
2 1 8 16 1
24 25
P3 P1
1 1
26
CY7C1049L-25VC
U2, U3
2
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
Item 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
Description DI9410_SOIC-BASE DIODE_SCHOTTKY_ SMB_2 -2A, 20V H1026_SMD-BASE HEADER2_100 MILBASE HEADER2_JUMPERBASE HEADER3S-BASE HEADER4-BASE HEADER5X2-BASE HEADER5_100 MILBASE HEADER6_100 MILBASE HEADER_8X2-BASE LC03_6_SOIC-BASE LT1585_TO220_HORZ-B ASE LTC1422_SOIC-BASE MAX202_1_SOIC16BASE MC68340_1 MMBT3904 MOLEX53460_0611_2 MM- BASE MOUNTING_HOLE150 MIL OSC_4PIN_25.0000M HZ- BASE
Vendor Part Number DI9410 DIGI-KEY -B220DICT-ND H1026 DIGI-KEY S1011-36ND DIGI-KEY S1011-36ND DIGI-KEY S1011-36ND DIGI-KEY S1011-36ND DIGI-KEY S2012-36ND DIGI-KEY S1011-36ND DIGI-KEY S1011-36ND HEADER_8X2 LC03_6 LT1585CT-3.3 LTC1422CS8 MAX202CSA MOTOROLA MC68340 MMBT3904 53460-0611 PART OF PCB DIGIKEY CTS CTX171-ND
Reference Designator Q2 D4 T5 J25 J19 J9-J16 J18 J3 J23 J27 J26 U4-U35 U68 U67 U1 U36 Q1 J4, J28 M2 Y2
Qty 1 1 1 1 1 8 1 1 1 1 1 32 1 1 1 1 1 2 1 1
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
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DSLAM REFERENCE DESIGN: LINE CARD
Item 47 48
Description OSC_4PIN_3.6864MH Z-B ASE OSC_TTL_DIP2.048MHZ , 50 PPM, CHA OSC_TTL_DIP25.0000M HZ, 100 PPMA PBNO_VERT_6MMBASE PWRBLOCK_2-BASE RESISTOR-.01, 1%, 1206 RESISTOR-.10, 5%, 1210 RESISTOR-.47, 1%, 805 RESISTOR-0, 5%, 805 RESISTOR-1.0, 5%, 805
Vendor Part Number DIGIKEY CTS CTX154-ND K1150BA
Reference Designator Y3 Y1
Qty 1 1
49
DIGI-KEY -- CTX176ND DIGIKEY -- P8009SND TERMINAL BLOCK IRC-TT LRC-LR120601-R01 0-F IRC-TT LRC-LR121001-R10 0-F DIGI-KEY -PDCT-ND DIGI-KEY -PACT-ND DIGI-KEY -PBCT-ND
Y4
1
50 51 52 53 54 55 56
SW1, SW2 P4 R44 R37, R41-R43, R45, R266R270 R13-R20 R30-R33 R156, R157, R164, R165, R172, R173, R180, R181, R188, R189, R196, R197, R204, R205, R212, R213 R87-R94 R50, R51, R56, R57, R62, R63, R68, R69, R75, R78, R80, R81, R222, R225 R38 R1-R4, R11, R49, R52, R55, R58, R61, R64, R67, R70, R73, R76, R79, R82, R84-R86, R99, R152-R154, R224
2 1 1 10 8 4 16
57 58
RESISTOR-1.00M, 1%, 603 RESISTOR-1.0K, 5%, 603 RESISTOR-10, 5%, 603 RESISTOR-100, 5%, 603
DIGI-KEY -PMHCT-ND DIGI-KEY -PGCT-ND DIGI-KEY -P10GCT-ND DIGI-KEY -PGCT-ND
8 14
59 60
1 25
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RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
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DSLAM REFERENCE DESIGN: LINE CARD
Item 61
Description RESISTOR-100K, 5%, 603
Vendor Part Number DIGI-KEY -P100KGCT-ND
Reference Designator R100, R161, R169, R177, R185, R193, R201, R209, R217, R230, R233, R236, R239, R242, R245, R248, R251 R219, R263 R97, R98, R264 R102, R103, R105, R106, R108, R109, R111, R112, R114, R115, R117, R118, R120, R121, R123, R124, R126, R127, R129, R130, R132, R133, R135, R136, R138, R139, R141, R142, R144, R145, R147, R148 R101, R104, R107, R110, R113, R116, R119, R122, R125, R128, R131, R134, R137, R140, R143, R146 R47, R53, R54, R59, R60, R65, R66, R71, R72, R74, R77, R83 R158, R166, R174, R182, R190, R198, R206, R214 R39 R258, R259 R46, R48 R5-R10, R12 R260 R220, R221 R21
Qty 17
62 63 64
RESISTOR-10K, 1%, 603 RESISTOR-10M, 5%, 1206 RESISTOR-12.7, 1%, 603
DIGI-KEY -PGCT-ND DIGI-KEY -PECT-ND DIGI-KEY -P12.7HCT-ND
2 3 32
65
RESISTOR-18.2, 1%, 603
DIGI-KEY -P18.2HCT-ND
16
66 67 68 69 70 71 72 73 74
RESISTOR-2.0K, 5%, 603 RESISTOR-2.2, 1%, 805 RESISTOR-2.43K, 1%, 603 RESISTOR-20.0, 1%, 603 RESISTOR-200, 5%, 603 RESISTOR-270, 5%, 603 RESISTOR-3.3, 1%, 805 RESISTOR-33, 5%, 603 RESISTOR-4.75K, 1%, 603
DIGI-KEY -PGCT-ND DIGI-KEY -PDCT-ND DIGI-KEY -PHCT-ND DIGI-KEY -P20.0HCT-ND DIGI-KEY -PGCT-ND DIGI-KEY -PGCT-ND DIGI-KEY -PDCT-ND DIGI-KEY -PGCT-ND DIGI-KEY -PGCT-ND
12 8 1 2 2 7 1 2 1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
41
RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
Item 75
Description RESISTOR-4.7K, 5%, 603
Vendor Part Number DIGI-KEY -PGCT-ND
Reference Designator R22, R27-R29, R34-R36, R95, R96, R149-R151, R159, R167, R175, R183, R191, R199, R207, R215, R223, R232, R235, R238, R241, R244, R247, R250, R253, R272, R273 R227, R228 R23-R26 R155, R160, R162, R163, R168, R170, R171, R176, R178, R179, R184, R186, R187, R192, R194, R195, R200, R202, R203, R208, R210, R211, R216, R218, R231, R234, R237, R240, R243, R246, R249, R252, R254-R257, R261, R262, R265, R271 R40 R226, R229 RN1-RN6, RN15
Qty 31
76 77 78
RESISTOR-430, 5%, 603 RESISTOR-49.9, 1%, 603 RESISTOR-56, 5%, 603
DIGI-KEY -PGCT-ND DIGI-KEY - P49.9HCT-ND DIGI-KEY -PGCT-ND
2 4 40
79 80 81
RESISTOR-6.81K, 1%, 603 RESISTOR-750, 5%, 603 RES_ARRAY_4_SMD4.7K RES_ARRAY_4_SMD56 RJ45-BASE SSF_LXH5147-LGD SSF_LXH5147-LID SUNIDUPLEX_SERIA L_PB GA-BASE T9021_-BASE TST_PT-BASE
DIGI-KEY -P6.81KHCT-ND DIGI-KEY -PGCT-ND DIGI-KEY -Y4ND DIGI-KEY -Y4ND RJ45 SSF-LXH5147LGD SSF-LXH5147LID PM7350-PI T9021 DIGI-KEY S1011-36ND
1 2 7
82
RN7-RN14
8
83 84 85 86 87 88
J2 D3 D1, D2 U64 U38-U41 TP7
1 1 2 1 4 1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
42
RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
Item 89 90 91 92 93 94 95 96 97 98 99 100
Description TST_PT-BASE TST_PT-BASE TST_PT-BASE TST_PT-BASE TST_PT-BASE TST_PT-BASE TST_PT-BASE TST_PT-BASE TST_PT-BASE TST_PT-BASE ZPACK5X22FH_ASCP CI_2 MM ZPACK5X22FH_BSCP I_2M M
Vendor Part Number DIGI-KEY S1011-36ND DIGI-KEY S1011-36ND DIGI-KEY S1011-36ND DIGI-KEY S1011-36ND DIGI-KEY S1011-36ND DIGI-KEY S1011-36ND DIGI-KEY S1011-36ND DIGI-KEY S1011-36ND DIGI-KEY S1011-36ND DIGI-KEY S1011-36ND 352068-1 352152-1
Reference Designator TP8, TP15, TP18, TP23 TP3, TP10, TP16, TP25 TP1, TP6 TP2 TP12 TP13 TP9 TP20 TP4, TP5, TP11, TP14, TP17, TP21, TP22, TP24, TP26 TP19 J1 J5
Qty 4 4 2 1 1 1 1 1 9 1 1 1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
43
RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
NOTES
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
44
RELEASED REFERENCE DESIGN PMC-1990354 ISSUE 3
PM7350 S/UNI-DUPLEX
DSLAM REFERENCE DESIGN: LINE CARD
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2000 PMC-Sierra, Inc. PMC-1990354 (R3) Issue date: November 2000
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE

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